Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/30/2024, 11/07/2024, 12/18/2024 & 05/08/2025 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-12, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sumida et al. (Pub. No.: US 2016/0336443 A1).
Regarding Claim 11, Sumida et al. discloses a semiconductor device, comprising: a substrate (Par. 0033; Figs. 1-13 – substrate SB); an epitaxial layer, on the substrate (Par. 0033; Figs. 1-13 – epitaxial layer EP);
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a gate structure, in the epitaxial layer, wherein the gate structure has a first part, a second part and a third part from bottom to top, a width of the third part is greater than a width of the second part, and a width of the first part is greater than a width of the second part (Par. 0033-0037; Figs. 1-13 – gate structure comprising insulating film TF, gate insulating film GF, gate electrode GE; first part corresponds to lower electrode GD2, second part corresponds to some lower portion of upper electrode GD1, third part corresponds to some upper portion of upper electrode GD1); a source electrode, on the epitaxial layer (Par. 0033-0042; Figs. 1-13 – source electrode SE); and a drain electrode, below the substrate (Par. 0042; Figs. 1-13 – drain electrode is not shown but it is mentioned to be formed underside of the substrate SB).
Regarding Claim 12, Sumida et al., as applied to claim 11, discloses
the semiconductor device, wherein the epitaxial layer comprises: a source region, adjacent to the third part of the gate structure, wherein a bottom of the third part of the gate structure is higher than a bottom of the source region (Par. 0033-0042; Figs. 1-13 – source region SR; the third part of the gate structure is defined such that a bottom of the third part of the gate structure is higher than a bottom of the source region); and a well region, adjacent to the source region and the gate structure (Par. 0033-0042; Figs. 1-13 – well region BR (base region)).
Regarding Claim 14, Sumida et al., as applied to claim 11, discloses
the semiconductor device, wherein the epitaxial layer comprises: a source region, adjacent to the third part of the gate structure (Par. 0033-0042; Figs. 1-13 – source region SR; the third part of the gate structure is defined such that the source region is adjacent to the third part of the gate structure); and a well region, adjacent to the source region and the gate structure, wherein the third part of the gate structure is in contact with the well region and the source region (Par. 0033-0042; Figs. 1-13 – well region BR (base region); the third part of the gate structure is defined such that it is in contact with the well region and the source region).
Allowable Subject Matter
Claims 1-10 are allowed. The following is an examiner's statement of reasons for allowance:
Regarding Claim 1: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by a method of manufacturing a semiconductor device, comprising: forming an epitaxial layer on a substrate; forming a well region and a source region in the epitaxial layer; forming a first trench in the epitaxial layer, a corner of the first trench having a round corner protruding to the well region; forming a second trench in the epitaxial layer, a bottom of the second trench being higher than a bottom of the first trench, and a width of the second trench being greater than a width of the first trench; and forming a gate structure in the first trench and the second trench.
The most relevant prior art reference due to Koai et al. (Patent No.: US 6,159,299) substantially discloses a method of manufacturing a semiconductor device, comprising: forming an epitaxial layer on a substrate (Par. 0071-0082; Figs. 1-13 (especially see Fig. 5) – epitaxial layer EP; substrate SB); ; forming a well region and a source region in the epitaxial layer (Par. 0071-0082; Figs. 1-13 (especially see Fig. 13) – well region BR; source region SR); forming a first trench in the epitaxial layer Par. 0071-0082; Figs. 1-13 (especially see Fig. 9) – first trench D2 (ditch)); forming a second trench in the epitaxial layer, a bottom of the second trench being higher than a bottom of the first trench, and a width of the second trench being greater than a width of the first trench (Par. 0071-0082; Figs. 1-13 (especially see Fig. 9) – second trench D1 (ditch)); and forming a gate structure in the first trench and the second trench (Par. 0071-0082; Figs. 1-13 – gate structure comprising insulating film TF, gate insulating film GF, gate electrode GE)
This prior art, however, does not disclose a method of manufacturing a semiconductor device, comprising: a corner of the first trench having a round corner protruding to the well region.
Additionally, the prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. See form PTO-892.
However, none of these prior art references indicated above or the prior arts made of record in form PTO-892, disclose all the limitations of claim 1 (the individual limitations may be found in a plurality of prior arts but there is no motivation to combine). Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, claim 1 is deemed patentable over the prior arts.
Regarding Claims 2-10: these claims are allowed because of their dependency status from claim 1.
Allowable Subject Matter
Claims 13 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
1. Katou et al. (Pub No.: US 2013/0264637 A1) – This prior art teaches a semiconductor device, comprising: a substrate (SUB); an epitaxial layer (EPI), on the substrate; a gate structure (comprising FP, GIN & GE), in the epitaxial layer, wherein the gate structure has a first part, a second part and a third part from bottom to top, a width of the third part is greater than a width of the second part, and a width of the first part is greater than a width of the second part (Fig. 13); a source electrode, (EL2), on the epitaxial layer; and a drain electrode (EL1), below the substrate (Fig. 13).
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05/30/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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