DETAILED ACTION
This office action is in response to the application filed on April 30, 2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/30/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (EP 2,423,987) in view of Nagai (WO 2005/091388).
With respect to Claim 1, Jeong discloses (Fig. 10-11) most aspects of the current invention including a display panel, comprising:
a circuit substrate (175);
a bonding pattern (170) disposed on a substrate surface of the circuit substrate, wherein the bonding pattern has a first sidewall surface
a plurality of micro light emitting devices (135), respectively bonded to the circuit substrate through the bonding pattern, wherein the micro light emitting devices has a second sidewall surface, and the first sidewall surface and the second sidewall surface has a step difference in any direction parallel to the substrate surface
Additionally, although Jeong does not disclose a plurality of bonding patterns, disposed on a substrate surface of the circuit substrate, Jeong discloses wherein the micro light emitting structure is formed with inclined side surfaces due to the isolation etching process for dividing a plurality of chips into unit chip areas (see Fig 10; area 105), therefore forming a plurality of bonding patterns, disposed on a substrate surface of the circuit substrate and further having a plurality of micro light emitting devices, respectively bonded to the circuit substrate through the plurality of bonding patterns.
Furthermore, and in the same field of endeavor, Nagai teaches (see Fig. 4, step H1,J1,M1) a plurality of bonding patterns (layers 1004 in step M1), disposed on a substrate surface of a circuit substrate (30), a plurality of micro light emitting devices (6; comprising layers 10,12,14), respectively bonded to the circuit substrate through the plurality of bonding patterns. Nagai teaches the plurality of bonding patterns being metal plating allows them to be sufficient for supporting the plurality of micro light emitting devices and this arrangement ensures easy handling of the plurality of micro light emitting devices, thus the plurality of micro light emitting devices are suitable as an illumination light sources.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a plurality of bonding patterns, disposed on a substrate surface of the circuit substrate, and plurality of micro light emitting devices respectively bonded to the circuit substrate through the plurality of bonding patterns in the device of Jeong , as taught by Nagai because the plurality of bonding patterns being metal plating allows them to be sufficient for supporting the plurality of micro light emitting devices and this arrangement ensures easy handling of the plurality of micro light emitting devices, thus the plurality of micro light emitting devices are suitable as an illumination light sources.
With respect to Claim 2, Jeong discloses (Fig. 10-11) wherein an ohmic contact layer (150) is provided between each of the plurality of micro light emitting devices and corresponding one of the plurality of bonding patterns, and in the any direction parallel to the substrate surface, a first width of the ohmic contact layer is less than or equal to a second width of each of the plurality of bonding patterns
Claims 1-6, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Edmond (US 8,174,037) in view of Nagai (WO 2005/091388).
With respect to Claim 1, Edmond discloses (Fig. 14) most aspects of the current invention including a display panel, comprising:
a circuit substrate (21);
a bonding pattern (30) disposed on a substrate surface of the circuit substrate, wherein the bonding pattern has a first sidewall surface
a micro light emitting device (layers 26,22,27), respectively bonded to the circuit substrate through the bonding pattern, wherein the micro light emitting device has a second sidewall surface, and the first sidewall surface and the second sidewall surface has a step difference in any direction parallel to the substrate surface
Additionally, although Edmond does not disclose a plurality of bonding patterns, disposed on a substrate surface of the circuit substrate, and plurality of micro light emitting devices respectively bonded to the circuit substrate through the plurality of bonding patterns, Edmond does disclose wherein the wafer structure can be an extension of the individual diodes that are formed from the wafer, that can further define a plurality of individual diodes which are separated by the guidelines/cut line (47) (See Fig 5; column 8 lines 27-40).
Furthermore, and in the same field of endeavor, Nagai teaches (see Fig. 4, step H1,J1,M1) a plurality of bonding patterns (layers 1004 in step M1), disposed on a substrate surface of a circuit substrate (30), a plurality of micro light emitting devices (6; comprising layers 10,12,14), respectively bonded to the circuit substrate through the plurality of bonding patterns. Nagai teaches the plurality of bonding patterns being metal plating allows them to be sufficient for supporting the plurality of micro light emitting devices and this arrangement ensures easy handling of the plurality of micro light emitting devices, thus the plurality of micro light emitting devices are suitable as an illumination light sources.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a plurality of bonding patterns, disposed on a substrate surface of the circuit substrate, and plurality of micro light emitting devices respectively bonded to the circuit substrate through the plurality of bonding patterns in the device of Edmond, as taught by Nagai because the plurality of bonding patterns being metal plating allows them to be sufficient for supporting the plurality of micro light emitting devices and this arrangement ensures easy handling of the plurality of micro light emitting devices, thus the plurality of micro light emitting devices are suitable as an illumination light sources.
With respect to Claim 2, Edmond discloses (Fig. 14) wherein an ohmic contact layer (31) is provided between the micro light emitting device and corresponding bonding pattern, and in the any direction parallel to the substrate surface, a first width of the ohmic contact layer is less than or equal to a second width of the bonding pattern.
With respect to Claim 3, Edmond discloses (Fig. 14) wherein the ohmic contact layer (31) is cut off by a third sidewall surface, and the third sidewall surface is aligned with the first sidewall surface of the corresponding bonding pattern (30).
With respect to Claim 4, Edmond discloses (Fig. 14) wherein the second sidewall surface of the plurality of micro light emitting device (layers 26,22,27) is covered with an etching protection layer (71), and the etching protection layer extends from the second sidewall surface to cover the ohmic contact layer facing away from a surface of the circuit substrate.
With respect to Claim 5, Edmond discloses (Fig. 14) wherein a third width of the etching protection layer is less than or equal to the second width in the any direction parallel to the substrate surface.
With respect to Claim 6, Edmond discloses (Fig. 14) wherein the ohmic contact layer and the etching protection layer are coplanarly cut off at a cutoff plane.
With respect to Claim 8, Edmond discloses (Fig. 14) wherein the cutoff plane is aligned with the first sidewall surface.
Claims 7 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Edmond (US 8,174,037) in view of Nagai (WO 2005/091388) and in further view of Chen (US 2021/0126170).
With respect to Claim 7, Edmond in view of Nagai shows most aspects of the current invention. However, the combination of references do not show an embodiment wherein in the any direction parallel to the substrate surface, the cutoff plane is located between the first sidewall surface and the second sidewall surface, and the first sidewall surface and the second side wall surface has respectively a step difference with the cutoff plane.
On the other hand, and in the same field of endeavor, Chen teaches (see Fig. 9B) a bonding pattern (150) disposed on a substrate surface of a circuit substrate (10), wherein the bonding pattern has a first sidewall surface, a light emitting device (110h), respectively bonded to the circuit substrate through the bonding pattern, wherein the micro light emitting device has a second sidewall surface, and the first sidewall surface and the second sidewall surface has a step difference in any direction parallel to the substrate surface, an ohmic contact layer (140i; par 53) is provided between the micro light emitting device and corresponding bonding patterns, an etching protection layer (130) on the second sidewall surface of the micro light emitting device, and covering the ohmic contact layer (140i) facing away from a surface of the circuit substrate, wherein the ohmic contact layer and the etching protection layer are coplanarly cut off at a cutoff plane (130 and 140i coplanar outer edge) and wherein in the any direction parallel to the substrate surface, the cutoff plane (130 and 140i coplanar outer edge) is located between the first sidewall surface (sidewall surface of 150) and the second sidewall surface (sidewall surface of 110h), and the first sidewall surface and the second side wall surface has respectively a step difference with the cutoff plane. Chen teaches doing so allows the ohmic contact layer being directly connected to the bonding layer to conduct circuits on the substrate, thereby increasing the process efficiency (par 53).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein in the any direction parallel to the substrate surface, the cutoff plane is located between the first sidewall surface and the second sidewall surface, and the first sidewall surface and the second side wall surface has respectively a step difference with the cutoff plane in the device of Edmond in view of Nagai, as taught by Chen because this arrangement allows the ohmic contact layer being directly connected to the bonding layer to conduct circuits on the substrate, thereby increasing the process efficiency.
With respect to Claim 9, Edmond in view of Nagai shows most aspects of the current invention. Furthermore, Nagai teaches (see Fig. 4, step H1,J1,M1) wherein the second sidewall of each of the plurality of micro light emitting devices is covered with a first light reflection layer (22). However, the combination of references do not show an embodiment wherein the first light reflection layer extends from the second sidewall to cover the first sidewall.
On the other hand, and in the same field of endeavor, Chen teaches (see Fig. 5) a plurality of bonding patterns (layers 140), disposed on a substrate surface of a circuit substrate (10), wherein the bonding patterns has a first sidewall surface, a plurality of micro light emitting devices (110), respectively bonded to the circuit substrate through the plurality of bonding patterns, wherein the micro light emitting devices has a second sidewall surface, wherein the second sidewall of each of the plurality of micro light emitting devices is covered with a first light reflection layer (20), and the first light reflection layer extends from the second sidewall to cover the first sidewall (sidewall of 140). Chen teaches the first light reflection layer is used to electrically connect the micro light emitting devices to the substrate (par 39). Furthermore, Chen also teaches the first light reflection layer can climb to the outer edges of the bonding patterns (layer 140) and a protection layer (layer 130) more slowly to allow a buffering effect for the first light reflection layer (see par 49)
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the first light reflection layer extends from the second sidewall to cover the first sidewall in the device of Edmond in view of Nagai, as taught by Chen because the first light reflection layer is used to electrically connect the micro light emitting devices to the substrate and further this arrangement allows the first light reflection layer to climb to the outer edges of the bonding patterns (layer 140) and a protection layer (layer 130) more slowly to allow a buffering effect for the first light reflection layer.
With respect to Claim 10, Nagai teaches (see Fig. 4, step H1,J1,M1) a plurality of bonding patterns (layers 1004 in step M1), disposed on a substrate surface of a circuit substrate (30), a plurality of micro light emitting devices (6; comprising layers 10,12,14), respectively bonded to the circuit substrate through the plurality of bonding patterns, and wherein a second light reflection layer (24; see in step H1) is further disposed between each of the plurality of micro light emitting devices and corresponding one of the plurality of bonding patterns.
With respect to Claim 11, Nagai teaches (see Fig. 4, step H1,J1,M1) wherein each of the plurality of micro light emitting devices comprises a first-type semiconductor layer (10), an active layer (12), and a second-type semiconductor layer (14) stacked in a direction away from the circuit substrate, and the first light reflection layer (22) electrically contacts the second-type semiconductor layer, and is electrically insulated from the first-type semiconductor layer and the active layer (insulated by layer 1016; see in step J1)
Additionally, Chen teaches (see Fig. 5) wherein each of the plurality of micro light emitting devices comprises a first-type semiconductor layer (111), an active layer (112), and a second-type semiconductor layer (113) stacked in a direction away from the circuit substrate, and the first light reflection layer (20) electrically contacts the second-type semiconductor layer, and is electrically insulated from the first-type semiconductor layer and the active layer (insulated by layer 130)
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Edmond (US 8,174,037) in view of Nagai (WO 2005/091388) and in further view of Chen (US 2021/0126170) and Kwon (US 2020/0119244).
With respect to Claim 12, Edmond in view of Nagai and in further view of Chen shows most aspects of the current invention. However, the combination of references do not show an embodiment wherein a first insulation layer and a second insulation layer are respectively disposed on two opposite sides of the first light reflection layer on each of the plurality of micro light emitting devices.
On the other hand, and in the same field of endeavor, Kwon teaches (see Fig. 1,4) a plurality of micro light emitting devices (120), respectively bonded to a circuit substrate (110), wherein the micro light emitting devices has a second sidewall surface, wherein the second sidewall of each of the plurality of micro light emitting devices is covered with a first light reflection layer (123P), and further wherein a first insulation layer (111) and a second insulation layer (115) are respectively disposed on two opposite sides of the first light reflection layer on each of the plurality of micro light emitting devices. Kwon teaches the first insulation layer covers the plurality of micro light emitting devices and is used for protecting the elements thereunder and preventing an electrical short-circuit between layers in the plurality of micro light emitting devices (par 63) and further the second insulation layer is used to protecting the plurality of LEDs on the substrate (par 66).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein a first insulation layer and a second insulation layer are respectively disposed on two opposite sides of the first light reflection layer on each of the plurality of micro light emitting devices in the device of Edmond in view of Nagai and Chen, as taught by Kwon because the first insulation layer covers the plurality of micro light emitting devices and is used for protecting the elements thereunder and preventing an electrical short-circuit between layers in the plurality of micro light emitting devices and further the second insulation layer is used to protecting the plurality of LEDs on the substrate.
With respect to Claim 13, Kwon teaches (see Fig. 1,4) wherein the first insulation layer (111) contacts the second sidewall surface, and the second sidewall surface is completely covered by the first light reflection layer (123P) and the first insulation layer.
With respect to Claim 14, Chen teaches (see Fig. 5) wherein the second sidewall surface of each of the plurality of micro light emitting devices is covered with an etching protection layer (130), and the second side wall surface is completely covered by the first light reflection layer (20) and the etching protection layer (130).
Furthermore, although Chen does not show the etching protection layer is located between the first insulation layer and the second sidewall surface, Kwon teaches wherein a first insulation layer (111) and a second insulation layer (115) are respectively disposed on two opposite sides of the first light reflection layer on each of the plurality of micro light emitting devices. See comments stated above in Par. 34-35 with regards to Claim 12, which are considered repeated here.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to use an etching protection layer, as claimed by the applicant, in the device of Edmond in view of Nagai and in further view of Chen and Kwon, because etching protection layers are well-known in the semiconductor art for their use as means to provide protection to light emitting devices, as taught by Chen, and implementing the etching protection layer for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Conclusion
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/Q.A.B/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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