DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 30 April 2024, 24 April 2025 and 24 November 2025 were filed prior to the mailing date of this office correspondence. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of Invention II, claims 12-16 and 20 in the reply filed on 05 March 2026 is acknowledged.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Objections
Claim 12 and 16 are objected to because of the following informalities:
In claim 12, line 6: “a plurality of first atoms” should read:
-- a plurality of atoms --
In claim 16, line 2: “the plurality of first atoms” should read:
-- the plurality of atoms --
Appropriate correction is required. Also see the Note below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Mashino (US 20030235982) in view of Jang (Jang et. al., Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review, Material, 16, 7652, 2023).
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Annotated Fig. 5, Mashino.
Regarding claim 12, Mashino teaches, a manufacturing method of a substrate structure (Figs. 1 to 7, see Abstract), comprising:
providing a substrate (substrate 1, Fig. 1) with a plurality of through holes (through holes 2, Fig. 1) and a conductive layer (metallic sheet 5, Fig. 3);
bonding the substrate to the conductive layer (a step in which a piece of metallic foil or a metallic sheet 5 is made to adhere to the reverse surface of the silicon substrate 1, see Fig. 3, para. [0023]);
performing an electro-plating process (electrolytic plating is conducted while the piece of metallic foil 5 is used as a cathode as mentioned above and the metal 11 is precipitated in the through-holes so that these through-holes are plugged with the metal, see Figs. 3 to 5, para. [0025]) to respectively form a vertical conductive connector in the plurality of through holes; and
performing an annealing process (see Fig. 7) to diffuse a plurality of first atoms in the vertical conductive connector toward the substrate to form a bonding structure (high pressure annealing is conducted on the silicon substrate 1,…In the process of annealing, it is appropriate that the heating temperature is set at about 350 0C and the pressure is set at about 150 Mpa, para. [0027]).
Mashino does not explicitly teach, diffusing a plurality of first atoms in the vertical conductive connector toward the substrate. However, Jang teaches, a manufacturing method of a substrate structure including providing a substrate with a plurality of through holes (see Fig. 3); performing an electro-plating process to respectively form a vertical conductive connector in the plurality of through holes (Fig. 6); and performing an annealing process to diffuse a plurality of first atoms in the vertical conductive connector (TCB joins metal bumps via atomic diffusion in the solid state at temperatures typically between 200 and 400 0C, Page 14, third paragraph, see the Note below).
From the teachings of Mashino in para. [0027], process of annealing, it is appropriate that the heating temperature is set at about 350 0C and the pressure is set at about 150 Mpa, one of ordinary skill in the art would have known that annealing the metal layer at a temperature and a pressure would result in the metal atoms to diffuse over the interface barrier, which results in the formation of metal bonds and successful joining of a metal with a substrate. Jang teaches TSVs that go through thermal annealing after plating. Therefore, in view of the teachings of Jang, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the substrate of Mashino and to replace the temperature with a temperature as Jang taught in joining the metal layer so that it enables the metal atoms to diffuse over the interface barrier, which results in the formation of metal bonds. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in diffusing the atoms. Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success.
Note: the recited limitations in claim 12, “diffuse a plurality of first atoms” and in claim 16, “plurality of first atoms are inserted” do not contribute over the prior art because: (i) one of ordinary skill in the art would have known that annealing a metal layer at a temperature and a pressure would result in metal atoms diffusing over the interface barrier, which results in the formation of a metal bond. If applicant disagrees, see Jang, Page 14; (ii) the limitation does not provide any boundaries of protected subject matter “first atoms”.
Regarding claim 14, Mashino in view of Jang teaches the recited limitations with respect to claim 12. Mashino further teaches, the manufacturing method of the substrate structure according to claim 12, wherein a process temperature of the annealing process is 300 0C or greater (in the process of annealing, …the heating temperature is set at about 350 0C, para. [0027]).
Regarding claim 15, Mashino in view of Jang teaches the recited limitations with respect to claim 12. Mashino further teaches, the manufacturing method of the substrate structure according to claim 12, wherein the step before forming the vertical conductive connector does not comprise forming a seed layer (see Figs. 3 to 5).
Regarding claim 16, Mashino in view of Jang teaches the recited limitations with respect to claim 12. Jang further teaches, the manufacturing method of the substrate structure according to claim 15, wherein the plurality of first atoms are inserted into gaps of a material of the substrate (TCB joins metal bumps via atomic diffusion in the solid state… High temperatures and pressures cause metal atoms to diffuse over the interface barrier, Page 14, third paragraph). Therefore, in view of the teachings of Jang, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the substrate of Mashino and to replace the temperature with a temperature as Jang taught in joining the metal layer so that it enables the metal atoms to diffuse over the interface barrier, which results in the formation of metal bonds.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mashino in view of Jang as applied to claim 1 above, and further in view of Huang (US 20190313524).
Regarding claim 13, modified Mashino does not teach, an execution time of the annealing process. However, Huang teaches a manufacturing method of a substrate including providing a substrate with a plurality of through holes and a conductive layer (see annotated Fig. 2); bonding the substrate to the conductive layer (Fig. 2); performing an electro-plating process to respectively form a vertical conductive connector in the plurality of through holes (see via holes 110, Fig. 3), in which, the manufacturing method of the substrate structure according to claim 12, wherein an execution time of the annealing process is 30 minutes or greater (see Table 3). Therefore, in view of the teachings of Huang, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the substrate of Mashino and include 30 minutes of more annealing time as Huang taught in Table3 so that it enables precisely controlling the copper protrusion while annealing the conductive layer as Huang disclosed in para. [0220-0222].
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Mashino in view of Jang as applied to claim 1 above, and further in view of Koyama (US 20060191715).
Regarding claim 20, modified Mashino does not teach, bonding the conductive layer to the carrier layer. However, Koyama teaches a manufacturing method of a substrate including providing a substrate with a plurality of through holes and a conductive layer (see annotated Fig. 2C below); bonding the substrate to the conductive layer (Fig. 2C); forming a vertical conductive connector in the plurality of through holes (see via holes 15, Fig. 3A), in which,
the manufacturing method of the substrate structure according to claim 12, wherein the step before bonding the substrate to the conductive layer further comprises: providing a carrier layer (carrier 20, Fig. 2C); and bonding the conductive layer to the carrier layer (conductor layer 14a is formed by attaching metal foil such as copper foil on the releasable carrier 20, para. [0049]).
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Annotated Fig. 2C, Koyama.
Therefore, in view of the teachings of Koyama, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the substrate of Mashino and to a carrier layer 20 as Jang taught in Fig. 2C so that it enables precisely positioning the conductor layers relative to the via holes.
Conclusion
Prior art Wang (US 20150235899) teaches manufacturing method of a substrate structure, including, providing a substrate with a plurality of through holes and a conductive layer; performing an electro-plating process to respectively form a vertical conductive connector in the plurality of through holes; and performing an annealing process to form a bonding structure.
Prior art Brusso (US 20130208411) manufacturing method of a substrate structure, including, providing a substrate with a plurality of through holes and a conductive layer; performing an electro-plating process to respectively form a vertical conductive connector in the plurality of through holes; and performing an annealing process to form a bonding structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729
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