Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (hereinafter Kim, US 2024/0164091) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In regards to independent claim 1, Kim teaches a semiconductor device, comprising:
a source structure that includes a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer (Kim, Fig. 2B, SL1-3);
a gate stack structure on the source structure, the gate stack structure including dielectric patterns and conductive patterns that are alternately stacked (Kim Fig. 2B, GST1); and
a memory channel structure penetrating the gate stack structure (Kim, Fig. 2B, CS)
wherein the memory channel structure includes:
a channel layer (Kim, Fig. 2B, 187);
a data storage layer surrounding the channel layer (Kim, Fig. 2B, 183, [0068]); and
a blocking layer surrounding the data storage layer (Kim, Fig. 2B, CIP),
wherein the second source layer includes an inner sidewall directly contacting the channel layer (Kim, Fig. 2C, SL2, 187), and
wherein the third source layer includes an inner sidewall directly contacting the data storage layer (Kim, Fig. 2C, SL3, 183).
In regards to dependent claim 2, Kim teaches he semiconductor device of claim 1, wherein the second source layer includes a surface directly contacting the data storage layer (Kim, Fig. 2C, SL2, 183).
In regards to dependent claim 3, Kim teaches the semiconductor device of claim 2, wherein:
the third source layer includes a top surface directly contacting the blocking layer (Kim, Fig. 2C, CIP, SL3),
wherein a level of the top surface of the third source layer is higher than a level of the surface of the second source layer (Kim, Fig. 2C, Sl2, SL3).
In regards to dependent claim 4, Kim teaches the semiconductor device of claim 2, wherein the surface of the second source layer is positioned between the channel layer and the inner sidewall of the third source layer (Kim, Fig. 2C, Sl2, SL3, 187).
In regards to dependent claim 5, Kim teaches the semiconductor device of claim 2, wherein the surface of the third source layer is inclined (Kim, Fig. 2C, SL3).
In regards to independent claim 13, Kim teaches a semiconductor device, comprising:
a source structure that includes a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer (Kim, Fig. 2B, SL1-3);
a gate stack structure on the source structure, the gate stack structure including dielectric patterns and conductive patterns that are alternately stacked (Kim Fig. 2B, GST1); and
a memory channel structure penetrating the gate stack structure (Kim, Fig. 2B, CS),
wherein the memory channel structure includes:
a channel layer (Kim, Fig. 2B, 187);
a tunnel dielectric layer surrounding the channel layer (Kim, Fig. 2B, 183, [0068]);
a data storage layer surrounding the tunnel dielectric layer (Kim, Fig. 2B, 183, [0068]);; and
a blocking layer surrounding the data storage layer (Kim, Fig. 2B, CIP),
wherein the blocking layer is spaced apart from an upper surface of the second source layer (Kim, Fig. 2B, 183, [0068]),
wherein the second source layer includes a surface directly contacting the tunnel dielectric layer and the data storage layer (Kim, Fig. 2C, SL2, 183), and
wherein the third source layer includes a first top surface directly contacting the blocking layer (Kim, Fig. 2C, SL3, CIP).
Allowable Subject Matter
Claim 19-20 allowed.
Claim 6-12, 14-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
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