DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election, with traverse, of Species I of which claims read upon 1-10 in the “Response to Election / Restriction Filed -09/23/2026”, is acknowledged
This office action considers claims 1-20 pending for prosecution, of which, non-elected claims 11-20 are withdrawn, and elected claims 1-10 are examined on their merits.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (10; Fig 7B; [0051] or C 18, L 18-37) = (element 100; Figure No. 4; Paragraph No. [0036]) or Column No 18, Line Nos. 18-17. For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” or “Column No, Line Nos" shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation, for example in this document Yamaguchi, may not be preceded by the inventor tag, wherein the other reference citation will, for example Min and/or Choi, carry inventor tag. These conventions are used throughout this document.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi; Hidenori et al. (US 20220406792 A1) hereinafter referenced as Yamaguchi; in view of MIN; Hyo-sun et al. (US 20170200616 A1); hereinafter referenced as Min; and in further view of CHOI; Jaybok et al. (US 20210104529 A1); hereinafter referenced as Choi.
Regarding Claim 1. Yamaguchi teaches a method of fabricating a semiconductor device (semiconductor device; [0050]), comprising (See the entire document Figs 18A to 26; paragraphs [0050-0090] along with other Figures and relevant disclosures, specifically, as cited below):
providing a substrate (10; Fig 7B; [0051] or 112; fig 28; [0043]) that includes a first region (M cell region; [0025]; first cited in Fig 3A; [0026]) and a second region (N peripheral region);
sequentially forming a target film (51; Fig 18B; [0068]), a first mask film (38), a second mask film (40,42), and an upper mask pattern (44) on the substrate (100);
forming a first (see below for “spacer”) pattern (481) that extends along a side surface of the upper mask pattern (48), wherein the first space pattern (481) includes a first line portion (481 at right-side) and a second line portion (481 at left-side) that extend in parallel across the first region (M) and the second region (N), and a folding portion (481 at bottom-side) that is bent from the first line portion (481 at right-side) and the second line portion (481 at left-side) on the second region (N) and that connects the first line portion (481 at right-side) and the second line portion (481 at left-side);
forming a (See below for “slit”) mask pattern (52/521/522/50) that covers the first (spacer) pattern (481) on the second region (N);
forming a first mask pattern (481; fig 25A-25B) by patterning the second mask film (38) using the (slit) mask pattern (52/521/522/50 ) and the first spacer pattern (481) as an etching mask;
forming a second spacer pattern (482) that extends along an inner side surface and an outer side surface of the first mask pattern ( 38);
forming a second mask pattern (22) by patterning the first mask film (38) using the second (spacer) pattern (482) as an etching mask; and
forming a plurality of target patterns (501,502; Figs 27A-27C; [0083]) by patterning the target film (51) using the second mask pattern (22) as an etching mask.
As indicated supra, the difference between Yamaguchi and the claim, is Yamaguchi does not expressly disclose first and/or second (see below for “spacer”) pattern (481/482) as spacer,
However, in the analogous art, Min teaches a method of fabricating a semiconductor device using a double patterning process ([0003), wherein ([0006]) a self-alignment double patterning (SADP) process and a self-alignment reversed patterning (SARP) process include operations of forming spacers on both sidewalls of each pattern of a set of patterns, selectively removing the patterns, and patterning an underlying layer using the spacers as an etch mask, which is being practiced at Figs 20A to21B; [0090-0092] as “a spacer layer 150 may be formed on the second etch stop layer 139. The spacer layer 150 may uniformly cover a top surface of the second etch layer 139, sidewalls of the third mask layer 137 which are exposed through the second opening OP1, sidewalls of the second etch stop layer 139 which are exposed through the first openings OP1, and a top surface of the first etch stop layer 135 which is exposed through the first and second openings O1 and O2” which are analogous to Yamaguchi formation of 481/482.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to include Mins’s process into Yamaguchi’s method and, thereafter the combination of (Yamaguchi and Min), thereby comprises the process steps of “Spacer” as claimed, since this inclusion, at least, provides patterning an underlying layer using spacer and patterns as an etch mask (Min [0006]).
The further difference between the combination of (Yamaguchi and Min) and the claim, is the combination does not expressly disclose mask pattern (52/521/522/50) as slit mask.
However, in the analogous art, Choi teaches a manufacturing method for an integrated circuit device including a buried channel array transistor (BCAT) ([0002) wherein ([0034]) the combination of first and second mask patterns 222P and 262P functions as silk etching masks with narrow trenches.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to include Choi’s process into modified Yamaguchi’s method and, thereafter the combination of (Yamaguchi, min and Choi), comprises the process steps as claimed, since this inclusion, at least, provides a thin film having an active layer of a single direction by applying a slit mask on which slits are arranged toward the single direction in order to fabricate a thin film having even channel widths.
Regarding Claim 2. the combination of (Yamaguchi, min and Choi) as applied to the claim 1, Yamaguchi, further teaches, wherein the target film (51; [0069]: contains a metal such as tungsten) includes a conductive film.
Regarding Claim 3. the combination of (Yamaguchi, min and Choi) as applied to the claim 1, Yamaguchi further teaches, wherein each of the target patterns includes a first line pattern (51 transformed by etch mask 481 at right-side and subsequently by 482/22) and a second line pattern (51 transformed by etch mask 481 at left-side and subsequently by 482/22) that extend in parallel across the first region and the second region, and a folding pattern (51 transformed by etch mask 481 at bottom-side and subsequently by 482/22)) that is bent from the first line pattern and the second line pattern and connects the first line pattern and the second line pattern.
Regarding Claim 4. the combination of (Yamaguchi, min and Choi) as applied to the claim 3, further teaches, wherein a width of the folding pattern (51 transformed by etch mask 481 at bottom-side and subsequently by 482/22) is greater (depicted in Figs 22A/23A/24A/25A) than a width of the first line pattern (51 transformed by etch mask 481 at right-side and subsequently by 482/22) and a width of the second line pattern (51 transformed by etch mask 481 at left-side and subsequently by 482/22).
Regarding Claim 5. the combination of (Yamaguchi, min and Choi) as applied to the claim 3, is silent on, wherein a pitch between the first line pattern (51 transformed by etch mask 481 at right-side and subsequently by 482/22) and the second line pattern (51 transformed by etch mask 481 at left-side and subsequently by 482/22) is 4 nm to 10 nm (Choi [0050]) .
Regarding Claim 6. the combination of (Yamaguchi, min and Choi) as applied to the claim 1, further teaches, (the method) further comprising:
removing the upper (in step of Fig 22A/22B) mask pattern (44) before forming the slit mask pattern (52/521/522/50 in Figs 24A-B).
Regarding Claim 7. the combination of (Yamaguchi, min and Choi) as applied to the claim 1, but does not expressly disclose, (the method) further comprising:
removing the upper mask pattern (44) “after” forming the slit mask pattern (52/521/522/50).
However, Applicant has not established the criticality of this sequence: removing the upper mask pattern (44) “after” forming the slit mask pattern”. Instead the previous claim 6 recites opposite sequence “removing the upper (in step of Fig 22A/22B) mask pattern before forming the slit mask pattern”,
Examiner would like to note that MPEP §2144.04.IV(C) guideline, where change in sequence is a Legal Precedent as Source of Supporting Rationale. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of removing the upper mask pattern (44) “after” forming the slit mask pattern (52/521/522/50) with a reasonable expectation of success since it has been held that changing in sequence involves only routine skill in the art. See Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959) (Prior art reference disclosing a process of making a laminated sheet wherein a base sheet is first coated with a metallic film and thereafter impregnated with a thermosetting material was held to render prima facie obvious claims directed to a process of making a laminated sheet by reversing the order of the prior art process steps.). See also In reBurhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results); In reGibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930) (Selection of any order of mixing ingredients is prima facie obvious.).
Regarding Claim 8. The combination of (Yamaguchi, min and Choi) as applied to the claim 1, Yamaguchi,further teaches, wherein the slit mask pattern (52/521/522/50) includes a photoresist (50/52; [0077-0078]).
Regarding Claim 9. The combination of (Yamaguchi, min and Choi) as applied to the claim 1, further teaches, wherein (in view of Min)
the second spacer pattern (482) includes an inner spacer pattern (Min 137; Figs 2A-21B; [0090-092) that extends along the inner side surface of the first mask pattern, and an outer spacer pattern (139) that extends along the outer side surface of the first mask pattern,
the inner spacer pattern (Min 137) includes a first inner line portion and a second inner line portion that extend in parallel (left and right in Min Fig 21B), a first inner folding portion that connects a first end of the first inner line portion and a first end of the second inner line portion, and a second inner folding portion that connects a second end of the first inner line portion and a second end of the second inner line portion, and
the outer spacer pattern (Min 139) extends along a circumference of the first inner line portion (137), a circumference of the second inner line portion, and a circumference of the second inner folding portion, and does not extend along a circumference of the first inner folding portion (P2 of 152 depicted in Fig 21A-B) .
Regarding Claim 10. The combination of (Yamaguchi, min and Choi) as applied to the claim 1, Yamaguchi further teaches, (the method) further comprising:
forming a plurality of active regions (between STI 114; Fig 28; [0042-0044]) within the substrate (112 (10)), wherein the plurality of active regions correspond to the plurality of target patterns (501,502; [0042]);
forming a plurality of direct contacts (116) that connect each of the target patterns with a first portion of each of the active regions;
forming a plurality of capacitor structures (140) on the substrate (10/112), wherein the plurality of capacitor structures (140) are connected to a second potion of each of the active regions; and
forming a plurality of gate electrodes (gate of transistor 142;[0044]: the gate electrode of the access transistor 142 corresponds to the word-lines 4 in diagrams such as FIG. 2, FIG. 3A, FIG. 3B, FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, FIG. 6A, and FIG. 6B) on the substrate (10/112), wherein the plurality of gate electrodes traverse ([0044]) between the first portion and the second portion of each of the active regions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
October 10, 2026
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