DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species F in the reply filed on 7/20/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 3, 12-16, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/20/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s)1-2, 4-11, 17-18 and 20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “a plurality of channel structures that are on side walls of the back gate line” is unclear if a plurality of channel structures is required on each side wall of the back gate line, or if some subset of the plurality of channel structures is on each side wall.
Regarding claim 1, the limitation “a word line that at least partially surrounds the plurality of channel structures” is unclear as to how it is related to “a plurality of channel structures that are on side walls of the back gate line and spaced apart from each other in a second direction that intersects the first direction.” Specifically, it would appear that the claimed plurality of channel structures is a plurality along the bit line in the X direction, as shown in Fig. 6A-B of applicant’s disclosure. It is therefore unclear how a single word line can partially surround the plurality of channel structures.
Regarding claim 1, the limitation “a bit line on a lower surface of each of the plurality of channel structures” is unclear as to a single bit line is on a lower surface of the plurality of channel structures or if the claim requires each channel structure to have a corresponding bit line, i.e. a plurality of bit lines.
Regarding claim 1, the limitation” each of the plurality of channel structures comprises: a first side wall facing the word line,” is unclear as to how it is related to “a plurality of channel structures that are on side walls of the back gate line and spaced apart from each other in a second direction that intersects the first direction.” Specifically, it would appear that the claimed plurality of channel structures is a plurality along the bit line in the X direction, as shown in Fig. 6A-B of applicant’s disclosure. It is therefore unclear how each channel structure has a first side wall facing the single word line.
Regarding claim 17, the limitation “A semiconductor device comprising:
a substrate;
a bit line that is on the substrate and extends in a first horizontal direction;
a plurality of channel structures that are electrically connected to the bit line and extend in a vertical direction from an upper surface of the bit line;
Regarding claim 17, the limitation “a back gate line that is on first side walls of the plurality of channel structures,” is unclear as to if the back gate is required to be on plural first side walls of each channel structure of if it is required to be a single first side wall of each channel structure.
Regarding claim 17, the limitation “a back gate insulating layer between the plurality of channel structures and the back gate line,” is unclear as to if a single back gate insulating layer is required between all of the channel structure and the back gate line, or if the claim requires each channel structure to have a corresponding back gate insulating layer, i.e. a plurality of back gate insulating layers.
Regarding claim 17, the limitation “a word line that is on second side walls of the plurality of channel structures, at least partially surrounds the plurality of channel structures,” is unclear as to how it is related to “a plurality of channel structures that are electrically connected to the bit line.” Specifically, it would appear that the claimed plurality of channel structures is a plurality along the bit line in the X direction, as shown in Fig. 6A-B of applicant’s disclosure. It is therefore unclear how a single word line can be on side walls and/or partially surround the plurality of channel structures.
Regarding claim 17, the limitation “a gate dielectric layer between the plurality of channel structures and the word line,” is unclear as to if a single gate dielectric layer is required between all of the channel structure and the word line, or if the claim requires each channel structure to have a corresponding gate dielectric layer, i.e. a plurality of gate dielectric layers.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 4-7, 9-11, 17-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (KR 20230113229, using machine translation provided herewith; herein “Yoo”) in view of Luo et al. (CN 113629054, using machine translation provided herewith; herein “Luo”)
Regarding claim 1, Yoo disclose in Fig. 1-4 and related text a semiconductor device comprising:
a back gate line (215, see pg. 3 para 5) that is on a substrate and extends in a first direction (e.g. D1);
a plurality of channel structures (137_1, 137_2, see pg. 3 para. 4) that are on side walls of the back gate line and spaced apart from each other in a second direction (e.g. D2) that intersects the first direction;
a word line (305_1/305_2, see pg. 3 para. 5) that at least partially surrounds the plurality of channel structures; and
a bit line (360, see pg. 3 para. 5) on a lower surface of each of the plurality of channel structures, wherein each of the plurality of channel structures comprises:
a first side wall facing the word line, and
a second side wall that faces the back gate line and is electrically connected to an edge of the first side wall,
wherein the second side wall is flat.
Yoo does not explicitly disclose wherein the first side wall is curved.
In the same field of endeavor, Luo teaches in Fig. 5m and related text a semiconductor device having each of the plurality of channel structures comprising
a first side, and
a second side wall that is electrically connected to an edge of the first side wall,
wherein the first side wall is curved, and
wherein the second side wall is flat (see Fig. 5m and page 12 para 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yoo by having he first side wall is curved, as taught by Luo, in order to achieve another well-known and acceptable shape of a channel structure in the semiconductor device. Additionally, it would have been obvious since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
Regarding claim 2, Yoo further discloses wherein a horizontal width of each of the plurality of channel structures decreases from an upper portion of each of the plurality of channel structures to a lower portion of each of the plurality of channel structures (note that one can arbitrarily choose portions at which to take the width such that the claimed limitation is met).
Regarding claim 4, Yoo further discloses a lower back gate capping layer (270) between the back gate line and the bit line; and a lower word line capping layer (330) between the word line and the bit line.
Regarding claim 5, the combined device shows wherein the first side wall of each of the plurality of channel structures has a circular-arc shape or an elliptical-arc shape (see Luo, Fig. 5m).
Regarding claim 6, the combined device shows wherein the plurality of channel structures comprises a first channel structure and a second channel structure, and wherein:
the first channel structure faces a first side wall from among the side walls of the back gate line; and
the second channel structure faces a second side wall from among the side walls of the back gate line,
the first channel structure is symmetrical to the second channel structure with respect to the back gate line, and
the back gate line is between the first channel structure and the second channel structure (Luo: see Fig. 5m; Yoo: see Figs. 1-3).
Regarding claim 7, Yoo further discloses a back gate insulating layer (207, see pg. 3 para. 6) between the plurality of channel structures and the back gate line.
Regarding claim 9, Yoo further discloses
a plurality of conductive contact patterns (605, see pg. 3 para. 6) that are respectively on a plurality of upper surfaces of the plurality of channel structures; and
a separation insulation pattern (186, see pg. 3 para. 6) between the plurality of conductive contact patterns (see pg. 15 para. 5 through pg. 16 para. 2).
Regarding claim 10, Yoo further discloses wherein the back gate line and the word line are spaced apart from the plurality of conductive contact patterns, and wherein the semiconductor device further comprises:
an upper back gate line capping layer (540) on an upper portion of the back gate line; and
an upper word line capping layer (545) on an upper portion of the word line.
Regarding claim 11, Yoo further discloses
a capacitor insulating layer on the plurality of conductive contact patterns; and
a capacitor structure that extends into the capacitor insulating layer and is electrically connected to a conductive contact pattern from among the plurality of conductive contact patterns (see pg. 15 para. 5 through pg. 16 para. 2).
Regarding claim 17, Yoo disclose in Fig. 1-4 and related text a semiconductor device comprising:
a substrate (100);
a bit line (360, see pg. 3 para. 5) that is on the substrate and extends in a first horizontal direction (e.g. D2);
a plurality of channel structures (137_1, 137_2, see pg. 3 para. 4) that are electrically connected to the bit line and extend in a vertical direction from an upper surface of the bit line;
a back gate line (215, see pg. 3 para 5) that is on first side walls of the plurality of channel structures and extends in a second horizontal direction (e.g. D1) that intersects the first horizontal direction;
a back gate insulating layer (207, see pg. 3 para. 6) between the plurality of channel structures and the back gate line;
a word line (305_1/305_2, see pg. 3 para. 5) that is on second side walls of the plurality of channel structures, at least partially surrounds the plurality of channel structures, and extends in the second horizontal direction;
a gate dielectric layer (297, see pg. 3 para. 6) between the plurality of channel structures and the word line;
a conductive contact pattern (605, see pg. 3 para. 6) that is on the plurality of channel structures and is electrically connected to a first channel structure among the plurality of channel structures; and
a capacitor structure that is on the conductive contact pattern and electrically connected to the conductive contact pattern (see pg. 15 para. 5 through pg. 16 para. 2),
wherein each of the plurality of channel structures comprises a first side wall that contacts the gate dielectric layer and a second side wall that contacts the back gate insulating layer,
wherein the second side wall is flat.
Yoo does not explicitly disclose wherein the first side wall is curved.
In the same field of endeavor, Luo teaches in Fig. 5m and related text the remaining claimed limitations in the same manner and for the same reasons as applied to claim 1 above.
Regarding claim 18, Yoo further discloses wherein a horizontal width of each of the plurality of channel structures decreases from an upper portion of each of the plurality of channel structures to a lower portion of each of the plurality of channel structures (note that one can arbitrarily choose portions at which to take the width such that the claimed limitation is met).
Regarding claim 20, the combined device shows the plurality of channel structures comprises a second channel structure, and wherein:
the first channel structure faces a first side of the back gate line,
the second channel structure faces a second side of the back gate line,
the first channel structure is symmetrical to the second channel structure with respect to the back gate line, and
the first channel structure and the second channel structure are spaced apart in the first horizontal direction (Luo: see Fig. 5m; Yoo: see Figs. 1-3).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Luo, as applied to claim 7 above, and further in view of Lee et al. (US 20230187548; herein “Lee”).
Regarding claim 8, Yoo further discloses a gate dielectric layer (297, see pg. 3 para. 6) between the plurality of channel structures and the word line, but does not disclose
a first side wall of a first portion of the gate dielectric layer overlaps the plurality of channel structures in the first direction and is curved, and
a second side wall of a second portion of the gate dielectric layer is flat.
In the same field of endeavor, Lee teaches in Fig. 3 and related text a semiconductor device with a gate dielectric layer (Gox1/Gox2, see [0051]) between the plurality of channel structures (AP1/AP2, see [0040]) and the word line (WL1/WL2, see [0048]), wherein
a first side wall of a first portion of the gate dielectric layer overlaps the plurality of channel structures in the first direction and is conformal to the channel structures, and
a second side wall of a second portion of the gate dielectric layer is flat (see Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yoo by having a first side wall of a first portion of the gate dielectric layer overlaps the plurality of channel structures in the first direction and is curved, and a second side wall of a second portion of the gate dielectric layer is flat, as shown by Lee, in order to provide a manufacturing method which provides a structure with improved characteristics and integration density (see [0003]-[0004]). The limitation “a first side wall of a first portion of the gate dielectric layer overlaps the plurality of channel structures in the first direction and is curved” is therefore taught by the combination of the conformal gate dielectric, as shown by Lee, and the curved first side wall of the channel structures, as shown by Luo.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896
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