Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group I, claims 1-10 in the reply filed on June 10th, 2026, is acknowledged. Non-elected invention of Group II, claims 11-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Group I, claims 1-10 as follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 30th, 2024; June 04th, 2025; August 01st, 2025; October 02nd, 2025; and June 10th, 2026 have been considered by the examiner.
Drawings
The drawings filed on 04/30/2024 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-4 and 6 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Kim (US 2021/0066244, hereinafter as Kim ‘244).
Regarding Claim 1, Kim ‘244 teaches a system-in-package (SIP) (100D; [0085]), comprising:
a general-purpose memory die (Fig. 13, (130b); [0023]);
a near-memory compute die (Fig. 13, (120); [0023]); and
an inter-space filler (Fig. 13, (150); [0023]) in between the general-purpose memory die (130b) and the near-memory compute die (120).
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Fig. 13 (Kim ‘244)
Regarding Claim 2, Kim ‘244 teaches the general-purpose memory die (130b) having a first size and the near-memory compute die (120) having a second size different from the first size (see Fig. 13).
Regarding Claim 3, Kim ‘244 teaches a base die (110; [0023]) supporting the general-purpose memory die and the near-memory compute die. Examiner considers the package substrate (110) is a base die.
Regarding Claim 4, Kim ‘244 teaches a wafer/substrate/interposer (110; [0023]) supporting the general-purpose memory die (130b) and the near-memory compute die (120).
Regarding Claim 6, Kim ‘244 the inter-space filler (150; [0023]) comprises a thermally conductive material (heat dissipation member (150); [0023]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘244 as applied to claim 1 above, and further in view of Wang (US 2004/0164390, hereinafter Wang ‘390).
Regarding Claim 5, Kim ‘244 teaches the general-purpose memory die (130b) and the near-memory compute die at least partially overlap with each other (120) (see Fig. 13).
Thus, Kim ‘244 is shown to teach all the features of the claim with the exception of explicitly the features: “the near-memory compute die is stacked on the general-purpose memory die”.
Wang ‘390 teaches the near-memory compute die (CPU; Fig. 2, (230); [0033]) is stacked on the general-purpose memory die (250; [0033]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘244 by having the near-memory compute die is stacked on the general-purpose memory die for the purpose of improving the efficiency of heat dissipation of the chips in the package (see para. [0014] and [0033]) as suggested by Wang ‘390.
Regarding Claim 7, Kim ‘244 teaches the inter-space filler (150) comprises a spin-on-carbon material (graphite, graphene or the like; [0043]).
Product by process limitation:
The expression “spin-on” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Regarding Claim 9, Wang ‘390 teaches the near-memory compute die comprises multiply-accumulate (MAC) compute blocks (CPU; [0033]). It would obviously appear that the central processing unit (CPU) (230; [0033]) is the multiply-accumulate (MAC) compute blocks.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘244 and Wang ‘390 as applied to claim 1 above, and further in view of Jang (US 2022/0208730, hereinafter Jang ‘730)
Regarding Claim 8, Wang ‘390 teaches an embedded molding compound (EMC) (322; [0035]) on the inter-space filler (320; [0034]) and on sidewalls of the near-memory compute die (230).
Thus, Kim ‘244 and Wang ‘390 are shown to teach all the features of the claim with the exception of explicitly the features: “a thermally insulative material (TIM) layer on the EMC; and a conductive/ceramic material layer on the TIM layer”.
Jang ‘730 teaches a thermally insulative material (TIM) layer (Fig. 13, (750); [0121] and [0138]) on the EMC (MD; [0099]); and a conductive/ceramic material layer (HS1; [0112]) on the TIM layer (see Fig. 13).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘244 and Wang ‘390 by having a thermally insulative material (TIM) layer on the EMC; and a conductive/ceramic material layer on the TIM layer for the purpose of achieving its high integration of the semiconductor package (see para. [0140]) as suggested by Jang ‘730.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘244 as applied to claim 1 above, and further in view of Jang (US 2023/0187329, hereinafter Jang ‘329)
Regarding Claim 10, Kim ‘244 is shown to teach all the features of the claim with the exception of explicitly the features: “a system-on-chip (SoC) communicably coupled to the general-purpose memory die”.
Jang ‘329 teaches a system-on-chip (SoC) (Fig. 8, (23); [0068]) communicably coupled to the general-purpose memory die (22; [0032]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘244 by having a system-on-chip (SoC) communicably coupled to the general-purpose memory die in order to provide a semiconductor package having improved reliability (see para. [0004]) as suggested by Jang ‘329.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraph numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Chiang et al. (US 2023/0317585 A1)
Shen et al. (US 2023/0246000 A1)
Low et al. (US 2010/0027233 A1)
Liu et al. (US 2009/0014860 A1)
Nishizawa et al. (US 2002/0011650 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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