Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the claim have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al., US 2017/0278462 A1 (hereinafter “Li”) in view of Xiang et al., US 2017/0221419 A1 (hereinafter “Xiang”).
Regarding claim 1, Li discloses a display panel (FIGS. 3 at [0038]-0039] organic light emitting display panel 300, and FIG. 8 at [0067], display device 800 includes the organic light emitting display panel), comprising:
a plurality of scan lines (FIG. 3, [0039]-[0040] scanning lines Scan(1), Scan(2)… Scan(m)) configured to respectively transmit a plurality of scan signals (FIG. 3, [0039]-[0040] and [0050] scanning lines Scan(1), Scan(2)… Scan(m));
a plurality of data lines (FIG. 3, [0039]-[0040] data lines Vdata(1), Vdata(2)… Vdata(n-1) and Vdata(n)) configured to respectively transmit a plurality of data signals (FIG. 3, [0039]-[0040] and [0050] data lines Vdata(1), Vdata(2)… Vdata(n-1) and Vdata(n)); and
a plurality of sub-pixels (FIGS. 2-5, pixel circuit 200 at [0038]-[0041], pixel circuit 400 at [0042], [0045]-[0046]), each of the sub-pixels being electrically connected to one of the plurality of scan lines and one of the data lines (FIGS. 2-5 pixels 200 and pixels 400 connected to scan lines at [0040]), and being configured to, during a data writing period (FIG. 6, and T11-T14 at [0052]-[0057]), receive one of the data signals transmitted by the one of the data lines based on one of the scan signals transmitted by the one of the scan lines (FIGS. 3 and 6-7, [0036]-[0044], [0051]-[0056] and [0058]-[0064]),
wherein the one of the data signals has a first level during the data writing period (FIGS. 6-7 and [0052]-[0056 ], period T13, level vdata), has a second level during a first period before or after the data writing period (FIGS. 6-7 and [0052]-[0056], period T11, level Vin), and has a third level during a second period between the first period and the data writing period (FIGS. 6-7 and [0052]-[0056], period T12, level Vbis); and
a first absolute value of a difference between a third voltage corresponding to the third level and a first voltage corresponding to the first level (FIG. 6 and [0053]-[0055], see annotation below) is less than a second absolute value of a difference between a second voltage corresponding to the second level and the first voltage (FIG. 6, and [0053]-[0055]; see annotation below).
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However, Li does not explicitly disclose the one of the scan signal lines has a high level during the data writing period and has a low level during the second period.
In the same field of endeavor, Xiang discloses the one of the scan signal lines has a high level during the data writing period (FIGS. 6-7 [0070]-[0074] and [0087]-[0095] and FIG. 6, SC2 is high when data2 is written in T14, FIG. 7, SC is high in t22 at t4) and has a low level during the second period (FIGS. 6-7 [0070]-[0074] and [0087]-[0095] and SC2 is low in FIG. 6 at T12, and FIG. 7 period after t2 through t3).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the drive scheme of Li to incorporate the driving as disclosed by Xiang because the references are within the same field of endeavor, namely, scan drivers for display devices and display driving schemes. The motivation to combine these references would have been to improve the resolution and evenness of brightness of the light emitting display panels (see Xiang at [0035] and [0118]-[0119]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Regarding claim 7, Li in view of Xiang discloses the display panel according to claim 1 (see above), wherein each of the sub-pixels (Li FIGS. 2 and 4, 200, and 400) comprises:
a light-emitting device (Li FIGS. 1, 2, and 4, organic light emitting diode D1 [0022]-[0025], [0032], [0036], [0050]);
a drive transistor (Li, DT) having an input terminal electrically connected to a first power supply terminal (Li, FIGS. 1, 2, and 4, DT connected to Pvdd [0023]-[0025], [0029], [0032], [0036]), and an output terminal electrically connected to the light-emitting device (Li, FIGS. 1, 2, and 4, DT output connected to D1 through N2 [0032], [0036]);
a switch transistor (Li, M2) having a control terminal electrically connected to one of the scan lines (Li, FIGS. 2 and 4, and [0034]-[0037], Scan line connected to control terminal of M2), an input terminal electrically connected to one of the data lines (Li, FIGS. 2 and 4, and [0034]-[0037], input terminal of M2 connected to Vdata data line), and an output terminal electrically connected to a control terminal of the drive transistor (Li, FIGS. 2 and 4, and [0034]-[0037], output terminal of M2 connected to control terminal of DT through N1); and
a first capacitor (Li, capacitor C) having a first terminal electrically connected to the control terminal of the drive transistor (Li, FIGS. 2 and 4, and [0034]-[0037], capacitor C top terminal connected to the control terminal of DT via N1), and a second terminal electrically connected to the output terminal of the drive transistor (Li, FIGS. 2 and 4, and [0034]-[0037], capacitor C bottom terminal connected to the output terminal of DT via N2).
Regarding claim 8, Li in view of Xiang discloses the display panel according to claim 7 (see above) wherein at least one of the sub-pixels (Li, FIGS. 1-2 and 4, subpixel 200 and 400) further comprises: a reset transistor (Li, M3) having a control terminal configured to receive a reset control signal (Li, FIGS. 2 and 4, control terminal of M3 receives signal from Ctrl2 at [0035]-[0037]), an input terminal configured to receive a reset signal (Li, FIGS. 2 and 4, input terminal of M3 receives signal from Col at [0035]-[0037]), and an output terminal electrically connected to the light-emitting device (Li, FIGS. 2 and 4, output terminal of M3 outputs to N2 connected to D1 at [0035]-[0037]); and
a compensation transistor (Li, FIGS. 2 and 4, M1) having a control terminal configured to receive a compensation control signal (Li, FIGS. 2 and 4, control terminal of M1 receives signal from Ctrl1 at [0035]-[0037]), an input terminal configured to receive a compensation signal (Li, FIGS. 2 and 4, input terminal of M3 receives signal from Vref at [0032]-[0037]), and an output terminal electrically connected to the control terminal of the drive transistor (Li, FIGS. 2 and 4, output terminal of M3 outputs signal to control terminal of DT at N1 at [0032]-[0037]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Xiang as applied to claim 1, and further in view of Lu et al., US 2024/0071321 A1 (hereinafter “Lu”).
Regarding claim 6, Li discloses the display panel according to claim 1 (see above).
However, Li does not explicitly disclose wherein a length of the data writing period is less than or equal to a length of the second period.
In the same field of endeavor, Lu discloses an OLED display panel and device (FIG. 1, AMOLED panel at [0043]-[0046]) wherein a length of the data writing period is less than or equal to a length of the second period (FIGS. 6 and 8, phases S3, the data write period, are equal to or less than reset phase S1 as discloses at [0065] and [0090] and as illustrated therein).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display device driving scheme of Li to incorporate the phase lengths as disclosed by Lu because the references are within the same field of endeavor, namely, display devices and display driving schemes. The motivation to combine these references would have been to improve display quality by reducing components and increasing pixels per inch (PPI) (see Lu at least at [0003]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display device driving scheme of Li to incorporate the phase lengths as disclosed by Lu because the references are within the same field of endeavor, namely, display devices and display driving schemes. The motivation to combine these references would have been to improve display quality by reducing components and increasing pixels per inch (PPI) (see Lu at least at [0003]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al., US 2017/0278462 A1, (hereinafter “Li”) in view of Kim et al., US 2018/0342217 A1 (hereinafter “Kim”).
Regarding claim 9, Li discloses a display control method ([0005]) a display panel (FIGS. 3 at [0038]-0039] organic light emitting display panel 300, and FIG. 8 at [0067], display device 800 includes the organic light emitting display panel), wherein the display panel comprises:
a plurality of scan lines (FIG. 3, [0039]-[0040] scanning lines Scan(1), Scan(2)… Scan(m)) configured to respectively transmit a plurality of scan signals (FIG. 3, [0039]-[0040] and [0050] scanning lines Scan(1), Scan(2)… Scan(m));
a plurality of data lines (FIG. 3, [0039]-[0040] data lines Vdata(1), Vdata(2)… Vdata(n-1) and Vdata(n)) configured to respectively transmit a plurality of data signals (FIG. 3, [0039]-[0040] and [0050] data lines Vdata(1), Vdata(2)… Vdata(n-1) and Vdata(n)); and
a plurality of sub-pixels (FIGS. 2-5, pixel circuit 200 at [0038]-[0041], pixel circuit 400 at [0042], [0045]-[0046]) each of the sub-pixels being electrically connected to one of the scan lines and one of the data lines (FIGS. 2-5 pixels 200 and pixels 400 connected to scan lines at [0040]), and being configured to, during a data writing period (FIG. 6, and T11-T14 at [0052]-[0057]), receive one of the data signals transmitted by the one of the data lines based on one of the scan signals transmitted by the one of the scan lines (FIGS. 3 and 6-7, [0036]-[0044], [0051]-[0056] and [0058]-[0064]),
the method comprising: obtaining a plurality of initial display grayscales respectively corresponding to the ones of the sub-pixels, and determining a grayscale interval corresponding to the each of the pixel columns based on the plurality of initial display grayscales (luminance level)(see Fig. 6; [0050, 0053]);
obtaining, based on the grayscale interval, a third voltage(Vbias) when one of the data signals transmitted by the one of the data lines and received by the ones of the sub-pixels has a third level (see Fig. 6; [0053-0055]).
controlling each of the ones of the sub-pixels to receive the one of the data signals during a data writing period (FIGS. 6-7 and [0052]-[0056 ], periods T11-T14), and controlling the one of the data signals to have a first level(Vdata) during the data writing period (FIGS. 6-7 and [0052]-[0056 ], period T13, level vdata), have a second level during a first period before or after the data writing period (FIGS. 6-7 and [0052]-[0056], period T11, level Vin), and have the third level during a second period between the first period and the data writing period (FIGS. 6-7 and [0052]-[0056], period T12, level Vbis),
wherein a first absolute value of a difference between the third voltage (Vbias) corresponding to the third level and a first voltage corresponding to the first level (FIG. 6 and [0053]-[0055], see annotation above) is less than a second absolute value of a difference between a second voltage(Vin) corresponding to the second level and the first voltage (FIG. 6, and [0053]-[0055]; see annotation above).
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However, Li does not disclose the obtaining occurs in a frame.
In the same field of endeavor, Kim teaches a frame period (see Fig. 6 and [0079]).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display device of Li to incorporate the determining and obtaining during a frame period of Kim because the references are within the same field of endeavor, namely, display devices and display driving schemes. The motivation to combine these references would have been to improve display quality, reduce light flickering and a reduction of power (see Kim at least at [0143] and [0150]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Claims 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al., US 2017/0278462 A1 (hereinafter “Li”) in view of in view of Lu et al., US 2024/0071321 A1 (hereinafter “Lu”) and further in view of Xiang et al., US 2017/0221419 A1 (hereinafter “Xiang”).
Regarding claim 10, Li discloses a display device (FIG. 8, organic light emitting display device 800 at [0067]), comprising:
a display panel (FIGS. 3 at [0038]-0039] organic light emitting display panel 300, and FIG. 8 at [0067], display device 800 includes the organic light emitting display panel); and
wherein the display panel comprises:
a plurality of scan lines (FIG. 3, [0039]-[0040] scanning lines Scan(1), Scan(2)… Scan(m)) configured to respectively transmit a plurality of scan signals (FIG. 3, [0039]-[0040] and [0050] scanning lines Scan(1), Scan(2)… Scan(m));
a plurality of data lines (FIG. 3, [0039]-[0040] data lines Vdata(1), Vdata(2)… Vdata(n-1) and Vdata(n)) configured to respectively transmit a plurality of data signals (FIG. 3, [0039]-[0040] and [0050] data lines Vdata(1), Vdata(2)… Vdata(n-1) and Vdata(n)); and
a plurality of sub-pixels (FIGS. 2-5, pixel circuit 200 at [0038]-[0041], pixel circuit 400 at [0042], [0045]-[0046]) each of the sub-pixels being electrically connected to one of the scan lines and one of the data lines (FIGS. 2-5 pixels 200 and pixels 400 connected to scan lines at [0040]), and being configured to, during a data writing period (FIG. 6, and T11-T14 at [0052]-[0057]), receive one of the data signals transmitted by the one of the data lines based on one of the scan signals transmitted by the one of the scan lines (FIGS. 3 and 6-7, [0036]-[0044], [0051]-[0056] and [0058]-[0064]),
wherein the one of the data signals has a first level during the data writing period (FIGS. 6-7 and [0052]-[0056 ], period T13, level vdata), has a second level during a first period before or after the data writing period (FIGS. 6-7 and [0052]-[0056], period T11, level Vin), and has a third level during a second period between the first period and the data writing period (FIGS. 6-7 and [0052]-[0056], period T12, level Vbis); and
a first absolute value of a difference between a third voltage corresponding to the third level and a first voltage corresponding to the first level (FIG. 6 and [0053]-[0055], see annotation above) is less than a second absolute value of a difference between a second voltage corresponding to the second level and the first voltage (FIG. 6, and [0053]-[0055]; see annotation above).
However, Li does not explicitly disclose a control module electrically connected to the display panel and configured to control the display panel to display, and the one of the scan signal lines has a high level during the data writing period and has a low level during the second period.
In the same field of endeavor, Lu discloses an OLED display panel and device (FIG. 1, AMOLED panel at [0043]-[0046]) comprising a control module electrically connected to the display panel and configured to control the display panel to display ([0082]-[0085] describing a controller component such as timing controller, CPU, signal processor, etc. connected to the display panel and controlling the pixels).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display device of Li to incorporate the controller as disclosed by Lu because the references are within the same field of endeavor, namely, display devices and display driving schemes. The motivation to combine these references would have been to improve display quality by reducing components and increasing pixels per inch (PPI) (see Lu at least at [0003]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
However, Li in view of Lu does not explicitly disclose the one of the scan signal lines has a high level during the data writing period and has a low level during the second period.
In the same field of endeavor, Xiang discloses the one of the scan signal lines has a high level during the data writing period (FIGS. 6-7 [0070]-[0074] and [0087]-[0095] and FIG. 6, SC2 is high when data2 is written in T14, FIG. 7, SC is high in t22 at t4) and has a low level during the second period (FIGS. 6-7 [0070]-[0074] and [0087]-[0095] and SC2 is low in FIG. 6 at T12, and FIG. 7 period after t2 through t3).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the drive scheme of Li in view of Lu to incorporate the driving as disclosed by Xiang because the references are within the same field of endeavor, namely, scan drivers for display devices and display driving schemes. The motivation to combine these references would have been to improve the resolution and evenness of brightness of the light emitting display panels (see Xiang at [0035] and [0118]-[0119]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Regarding claim 16, Li in view of Lu further in view of Xiang discloses the display device according to claim 10 (see above), wherein a length of the data writing period is less than or equal to a length of the second period (Lu at FIGS. 6 and 8, phases S3, the data write period, are equal to or less than reset phase S1 as discloses at [0065] and [0090] and as illustrated therein).
Allowable Subject Matter
Claims 2-5 and 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Li discloses the display panel according to claim 1 (see above), wherein the sub-pixels are arranged in a plurality of pixel columns (FIGS. 3 and 5, with pixels 200 and 400 arranged in column at [0038]-[0046]), and each of the pixel columns comprises ones of the sub-pixels electrically connected to one of the data lines (FIGS. 3 and 5, with pixels 200 and 400 connected to Vdata(1)… Vdata(n) at [0038]-[0045]).
Similarly, regarding claim 11, Li discloses the display device according to claim 10 (see above), wherein the sub-pixels are arranged in a plurality of pixel columns (FIGS. 3 and 5, with pixels 200 and 400 arranged in column at [0038]-[0046]), and each of the pixel columns comprises ones of the sub-pixels electrically connected to one of the data lines (FIGS. 3 and 5, with pixels 200 and 400 connected to Vdata(1)… Vdata(n) at [0038]-[0045]).
However, the cited prior art does not teach or disclose the following combination of limitations of claim 2, and similarly, claim 11:
the ones of the sub-pixels respectively have a plurality of initial display grayscales in a frame, a median value of a voltage corresponding to a maximum display grayscale among the initial display grayscales and a voltage corresponding to a minimum display grayscale among the initial display grayscales is taken as an intermediate voltage, and a third absolute value of a difference between the third voltage and the second voltage is less than or equal to the intermediate voltage.
By virtue of their dependency on claims 2 and claim 11, respectively, claims 3-5 and 12-15 are also objected to.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. US 11,232,747 B2;
Li et al., US 2023/0386391 A1;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARVESH J NADKARNI whose telephone number is (571)270-7562. The examiner can normally be reached 8AM-5PM M-F.
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/SARVESH J NADKARNI/Examiner, Art Unit 2621
/LUNYI LAO/Supervisory Patent Examiner, Art Unit 2621