DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A (Fig. 1-3, Claims 1-9, 11-20) in the reply filed on 07/31/2026 is acknowledged. The traversal is on the ground(s) that there is substantial overlap in common elements and that significant portion of the patents classified in either species would naturally be found when searching another specie. This is not found persuasive because the species are independent or distinct because of the reasons listed in Requirement for Restriction/Election 07/23/2026. In addition, these species are not obvious variants of each other based on the current record. There is a search and/or examination burden for the patentably distinct species as set forth above because at least the following reason(s) apply: the species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search queries); the prior art applicable to one species would not likely be applicable to the other species.
The requirement is still deemed proper and is therefore made FINAL.
Claim 10 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species D (Fig. 6), there being no allowable generic or linking claim.
Further, Claim 5 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species B (Fig. 4), there being no allowable generic or linking claim.
Applicant timely traversed the restriction (election) requirement in the reply filed on 07/31/2026.
Claim Objections
Claim 14 is objected to because of the following informalities: wherein the, in a third direction perpendicular to an upper surface of the substrate” should read “wherein, in a third direction perpendicular to an upper surface of the substrate”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-4, 6-9 and 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " a contact conductor layer on the metal-semiconductor compound layer" in and “the contact conductive layer”. There is insufficient antecedent basis for “the contact conductive layer” limitation in the claim. Since “conductor layer” and “conductive layer” are different terms, it is unclear whether the later recitation refers back to the contact conductor layer or a separate layer never introduced.
The same defect appears in:
Independent Claim 13
Independent Claim 17, which recites both “side surface of the contact layer and “a lower surface of the contact conductive layer”;
Dependent Claim 9, 19 and 20 which recite “the contact conductive layer.”
Claims 2-4, 6-8, 11, 12, 14-16 and 18 are rejected as depending from a rejected base claims.
Originally filed specification uses “contact conductive layer 186”. For the purposes of examination the Examiner will treat “a contact conductor layer” as –a contact conductive layer--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 11, 12, 17-20 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Lee et al. (US 2019/0074362 A1).
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Regarding Claim 1, Lee (Fig. 1-3, 14) discloses a semiconductor device comprising:
a substrate (100) including an active region (fin protrusion 100P) extending in a first direction (direction X);
a gate structure (120, 130) extending in a second direction (Y) on the substrate, the second direction intersecting the first direction; [0054, 0059-0060] (Fig. 1)
a plurality of channel layers (110, 210, 310) on the active region, spaced apart from each other in a third direction (Z direction), and surrounded by the gate structure (gate electrode wrap around wire pattern), the third direction (Z) being perpendicular to an upper surface of the substrate (100) [0041-0043, 0059];
a source/drain region (150) in a region at which the active region is recessed, on at least one side of the gate structure, and connected to the plurality of channel layers [0062. 0138-0141]; and
a contact plug (contact 170 and silicide 160) partially recessing the source/drain region (150) from an upper surface of the source/drain region and electrically connected to the source/drain region [0065], the contact plug including a metal-semiconductor compound layer (silicide film 160) along a recessed surface of the source/drain region [0076-0078]and a contact conductor layer (171 and 172] on the metal-semiconductor compound layer (160) [0066-0068], wherein
the metal-semiconductor compound layer (160) has a first thickness on a side surface of the contact conductive layer and a second thickness on a bottom surface of the contact plug, the second thickness (T2) being smaller than the first thickness (T1). (See annotated Fig. 2, 3),
Regarding Claim 4, Lee discloses the semiconductor device of claim 1, wherein
the plurality of channel layers comprise first to third channel layers sequentially arranged in the third direction, (wire patterns 110, 210, 310 “sequentially arranged in a third direction Z1)” [0041] and
a level of a lower end of the contact plug (lowermost part of silicide fim 160) is lower than a lower surface of the second channel layer (210). (Fig. 2).
Regarding Claim 11, Lee (Fig. 1-3, 14) discloses the semiconductor device of claim 1, further comprising:
a gate capping layer (145) on the gate structure; and
a contact spacer layer (142 between the gate capping layer and the contact plug (contact 170 and silicide 160) (Fig. 14)
Regarding Claim 12, Lee (Fig. 1-3) discloses the semiconductor device of claim 1, wherein
a level of an upper end of the metal-semiconductor compound layer (160) is equal to or higher than an upper surface of an uppermost one of the plurality of channel layers. (310) (Fig. 2).
Regarding Claim 17, Lee (Fig. 1-3) discloses a semiconductor device comprising:
a substrate (100) including an active region (fin protrusion 100P) extending in a first direction (direction X);
a gate structure (120, 130) extending in a second direction (Y) on the substrate, the second direction intersecting the first direction; [0054, 0059-0060] (Fig. 1)
first to third channel layers (310, 210, 110) on the active region, spaced apart from each other in a third direction (Z direction), sequentially arranged from top, and surrounded by the gate structure, the third direction being perpendicular to an upper surface of the substrate; [0041-0043] [0059]
a source/drain region (150) in a region at which the active region is recessed, on at least one side of the gate structure, and connected to the first to third channel layers; [0062], [0138-0141] and
a contact plug (170, 160) partially recessing the source/drain region (150) from an upper surface of the source/drain region and electrically connected to the source/drain region [0065], the contact plug including a metal-semiconductor compound layer (160) along a recessed surface of the source/drain region [0076-0078] and a contact conductor layer (171, 172) on the metal-semiconductor compound layer, [0065-0068] [0076-0078] wherein
the metal-semiconductor compound layer (160) has different thicknesses on a side surface of the contact conductive layer first direction thickness at third portion 163) and on a lower surface of the contact conductive layer (film thickness at the bottom), [0073], 0080] (See annotated Fig. 2, 3 as set forth in Claim 1) and wherein
a level of a lower end of the contact plug is lower than a level of a lower surface of the second channel layer (210). (H13<h12) [0083]
Regarding Claim 18, Lee (Fig. 1-3) discloses the semiconductor device of claim 17, wherein
a lower portion of the contact plug (170, 160) recessing the source/drain region (150) comprises a region having a width decreasing toward the substrate. (100). (H14<H15) [0074] contact width decreases from W12 to W11. [0073] First portion (170a) also has a rounded bottom (Fig. 2)
Regarding Claim 19, Lee (Fig. 1-3) discloses the semiconductor device of claim 17, wherein
the contact conductive layer (171, 172) has a bent portion along an upper end of the metal-semiconductor compound layer. (160). Outer wall of 170b within 190 and 195 is not aligned with the sidewall of 160 facing 171 [0086]. The 171 therefore steps inward at the upper end of 162. See Fig. 3
Regarding Claim 20, Lee (Fig. 1-3) discloses the semiconductor device of claim 17, wherein
the metal-semiconductor compound layer (160) has a first thickness on the side surface of the contact conductive layer (171, 172) and a second thickness on the lower surface of the contact conductive layer (171, 172), the second thickness being smaller than the first thickness. [0073, 0080](See rejection of Claim 1/annotated Fig. 2, and 3 T1>T2]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 13, 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2019/0074362 A1).
Regarding Claim 2, Lee (Fig. 1-3) discloses the semiconductor device of claim 1.
Lee does not explicitly disclose the second thickness is equal to or smaller than half of the first thickness.
Lee discloses that width of the third portion 163 is set by trench liner 175 that narrows the first portion (170at of the contact trench relative to the second portion (170tb) (W31<w32) [0149-0154). Lee teaches that this geometry trades contact area and contact resistance against the volume of semiconductor pattern 150 and the resulting stress on the channel wire pattern [0084-0085]. The width of the third portion 163 is thus a effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify semiconductor device in Lee such that the second thickness is equal to or smaller than half of the first thickness in order to balance contact resistance against the volume of the source/drain pattern and the channel stress it provides [0084-0085] and since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Further, the Examiner notes that the Applicant has not shown that the claimed ratio is critical or produces unexpected results, the specification presents it only as an example [0044]. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 3, Lee (Fig. 1-3) discloses the semiconductor device of claim 2.
Lee does not explicitly disclose the first thickness ranges from about 3 nm to about 10 nm.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify semiconductor device in Lee such that selecting the width of the third portion 163 plus the thickness of the second portion 162 within claimed range such that the first thickness ranges from about 3 nm to about 10 nm in order to balance contact resistance against the volume of the source/drain pattern and the channel stress it provides [0084-0085] and since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 276 (CCPA 1980).
Further, the Examiner notes that the Applicant has not shown that the claimed range is critical or produces unexpected results, the specification presents it only as an example [0044]. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 13, Lee (Fig. 1-3) discloses a semiconductor device comprising:
a substrate (100) including an active region (100P) extending in a first direction (X1); [0034]
a gate structure (120, 130) extending in a second direction (Y1) on the substrate (1), the second direction intersecting the first direction; [0059-0060]
a source/drain region (150) on at least one side of the gate structure [0062]; and
a contact plug (170, 160) partially recessing the source/drain region from an upper surface of the source/drain region and electrically connected to the source/drain region, the contact plug including a metal-semiconductor compound layer (160) along a recessed surface of the source/drain region and a contact conductor layer (171, 172) on the metal-semiconductor compound layer, [0076-0078) wherein
the contact plug (170,160) includes a lower region recessing the source/drain region (portion of a contact 170 below the upper surface of semiconductor pattern 150) and an upper region (portion within interlayer insulating film 190) on the lower region, and the lower region has a first width at an upper portion thereof (W12) and a second width at a lower portion thereof (W11), the second width being smaller than the first width,(boundary between 170a and 170b lies below the upper surface of the pattern (150) [0073-0074] and wherein
the metal-semiconductor compound layer (160) has a first thickness (X direction extent a third portion 163) in the first direction on a side surface of the contact conductive layer and a second thickness on a bottom surface of the contact plug (160 thickness at the bottom; See Annotated Claims 2 and 3 in Claim 1).
Lee does not explicitly disclose that the second thickness is equal to or smaller than half of the first thickness.
Lee discloses that width of the third portion 163 is set by trench liner 175 that narrows the first portion (170at of the contact trench relative to the second portion (170tb) (W31<w32) [0149-0154). Lee teaches that this geometry trades contact area and contact resistance against the volume of semiconductor pattern 150 and the resulting stress on the channel wire pattern [0084-0085]. The width of the third portion 163 is thus a effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify semiconductor device in Lee such that the second thickness is equal to or smaller than half of the first thickness in order to balance contact resistance against the volume of the source/drain pattern and the channel stress it provides [0084-0085] and since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Further, the Examiner notes that the Applicant has not shown that the claimed ratio is critical or produces unexpected results, the specification presents it only as an example [0044]. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 14, Lee (Fig. 1-3) discloses the semiconductor device of claim 13, wherein the,
in a third direction (Z) perpendicular to an upper surface of the substrate (100), a length of the lower region (portion of a contact 170 below the upper surface of semiconductor pattern 150) and a length of the source/drain region (150) below the lower region.
Lee further discloses that source drain below the plug extends only to a height H13, which lies between the top of 110 and the bottom of 210 [0083], the lower region therefore spans second and third wire patters (210, 310) and the spacing between them, while the pattern below spans first wire pattern (110) and part of one spacing (Fig. 2)
Lee does not explicitly disclose that relative lengths.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify semiconductor device in Lee such that length of the lower region is greater than a length of the source/drain region below the lower region in order to deepen the contact to reduce contact resistance [0084-0085] and since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 276 (CCPA 1980).
Regarding Claim 16, Lee (Fig. 1-3) discloses the semiconductor device of claim 13, wherein
a level of an upper end of the metal-semiconductor compound layer (160) is equal to or higher than the upper surface of the source/drain region. (150) (uppemeost part of 160 lies at H15, the upper surface of 150 [0074, 0081]
Claim(s) 6-9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2019/0074362 A1) in view of Tsai et al. (US 2021/0098583 A1)
Regarding Claim 6, Lee (Fig. 1-3) discloses the semiconductor device of claim 1.
Lee does not explicitly disclose a length from the upper surface of the source/drain region to a lower end of the contact plug ranges from about 10 nm to about 60 nm.
Tsai (Fig. 17B, 19) discloses a length from the upper surface of the source/drain region (38) to a lower end of the contact plug (60) [0080] (depth D1 of the contact opening in 38 whose bottom lies below the bottom surface of the bottom second layer 28) 0074] ranges from about 10 nm to about 60 nm. (D1 may be in range of about 23nm to about 70nm”) [0074].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify semiconductor device in Lee in view of Tsai such that a length from the upper surface of the source/drain region to a lower end of the contact plug ranges from about 10 nm to about 60 nm in order to increase the contact surface area between the contact plug and source/drain region and reduce source/drain contact resistance [0075, 0081 Tsai] [0084-0085 Lee] and since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 7, Lee (Fig. 1-3) discloses the semiconductor device of claim 1, wherein
the contact plug (160, 170) comprises a lower region (portion of a contact 170 below the upper surface of semiconductor pattern 150) recessing the source/drain region (150) and an upper region (portion within interlayer insulating film 190) on the lower region, and each of the lower region (W11 of 170a) and the upper region (W12) has a first width at a lower portion thereof and a second width at an upper portion thereof, (Fig. 3)
Lee does not explicitly disclose the first width being smaller than the second width.
Tsai (Fig. 19) discloses a contact plug (60) comprises a lower region () recessing the source/drain region (the second region of 60 which extends through 38)) and an upper region (first region of 60 which overlies the second region [0082]. The upper region extends through the interlayer dielectric layers (ILD1 46 and ILD0 40) [0074] on the lower region, and
each of the lower region and the upper region has a first width at a lower portion thereof and a second width at an upper portion thereof, and the first width being smaller than the second width. (First region of 60 narrows towards substrate 20 through ILD 1 and ILD 0. [See Fig. 19].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify semiconductor device in Lee in view of Tsai such that the first width being smaller than the second width since a change in shape of an element was considered a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP §2144.04) and since a simple substitution of one known source/drain contact opening profile for another with predicleble result KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) MPEP 2143 (1)(B)
Regarding Claim 8, Lee in view of Tsai discloses the semiconductor device of claim 7, wherein
the contact plug (160, 170) has a bent portion between the lower region and the upper region, the bent portion being a portion at which a width of the contact plug is discontinuously changed. (bent portion at the upper surface of 150, between the portion of the contact plug within 150 and the portion within 195 and 190; at that level, the outer wall of 170b within 190 and 195 “ is illustrated as not being aligned with” the sidewall of silicide film 160 facing 171. The width of the contact plug therefore steps abruptly instead of continuing along a single sidewall [0086 Lee] (Fig. 3. Lee)
Regarding Claim 9, Lee in view of Tsai discloses the semiconductor device of claim 7, wherein, in the lower region (portion of a contact 170 below the upper surface of semiconductor pattern 150), a width of the contact conductive layer (171 and 172) decreases toward the substrate. (100)
.
Regarding Claim 15, Lee (Fig. 1-3) discloses the semiconductor device of claim 13.
Lee does not explicitly disclose that a length of the lower region is about 10 nm or more.
Tsai (Fig. 17B, 19) a length of a lower region (second region of 60 which extends through 38) [0082] is about 10 nm or more. (D1 23nm-70nm) [0074).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify semiconductor device in Lee in view of Tsai such that a length of the lower region is about 10 nm or more in order to to increase the contact surface area between the contact plug and source/drain region and reduce source/drain contact resistance [0075] ,0081] (Lee 0084]
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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