DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because of the following informalities:
In Figures 1 and 5-16, change “P” to “PBL” for p-type buried layer 126.
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Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 125 (applicants’ specification, page 11, paragraph 41, lines 11, 12 of the paragraph). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Page 11, paragraph 41, line 6 of the paragraph: Change “Indium” to “indium”.
Page 11, paragraph 41, lines 11, 12 of the paragraph: Change 125 to 126 in each line, if applicants intended the PBL implant to have this reference number. Compare with “the p-type buried layer 126” in line 15.
Page 13, paragraph 46, lines 14 15: In each line, should “arsenic” be “indium”? P-type implants are discussed in this paragraph, and arsenic is an n-type implant.
Page 15, paragraph 50, line 3: Change “extending” to “extend”.
Page 15, paragraph 50, line 4: Change “valley” to “valleys”.
Appropriate correction is required.
Claim Objections
Claims 7 and 12 are objected to because of the following informalities:
Claim 7, line 2: Please provide antecedent basis for “the gate”.
Claim 12, line 2: Please provide antecedent basis for “the gate”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, which depends from claim 1: Claim 1 defines a gate electrode and a gate dielectric layer. Claim 7 refers to “the gate” without defining the gate or identifying the gate as the gate electrode or gate dielectric layer. Because the gate lacks antecedent basis, claim 7 is rejected as indefinite.
Regarding claim 12, which depends from claim 10: Claim 10 defines a gate electrode and a gate dielectric layer. Claim 12 refers to “the gate” without defining the gate or identifying the gate as the gate electrode or gate dielectric layer. Because the gate lacks antecedent basis, claim 12 is rejected as indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7, 10, 12, and 16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Nakagawa, U.S. Pat. Pub. No. 2010/0163987, Figures 1-3.
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Regarding claim 1: Nakagawa Figures 1-3 disclose a semiconductor device (1), comprising: a semiconductor layer (11, 12) over a semiconductor substrate (3), the semiconductor layer (11, 12) including a body region (11) having a first conductivity type and a drain drift region (12) having a second, opposite, conductivity type; a gate dielectric layer (17) over the body region (11) and extending over a junction between the body region (11) and the drain drift region (12); a gate electrode (18) over the gate dielectric layer (17); a drain region (15) having the second conductivity type in the drain drift region (12), the drain region (15) having a dopant density greater than a dopant density of the drain drift region (12); a field relief dielectric layer (16) over the drain drift region (12), the field relief dielectric layer (16) extending from the gate dielectric layer (17) toward the drain region (15) and having a thickness greater than the gate dielectric layer (17); and a field plate (22) located over the field relief dielectric layer (16) and between the gate electrode (18) and the drain region (15), the field plate (22) floating. Nakagawa specification ¶¶ 62-121.
Regarding claim 7, which depends from claim 1: Nakagawa discloses the field plate (22) extends between the drain region (15) and the gate [electrode] (18) by a distance that is at least twice a thickness of the field relief dielectric layer (16). See Nakagawa Figure 3. For purposes of this rejection, the distance is the collective distance of the field plate.
Regarding claim 10: Nakagawa Figures 1-3 disclose a semiconductor device (1), comprising: a semiconductor layer (11, 12) over a semiconductor substrate (3), the semiconductor layer (11, 12) including a body region (11) having a first conductivity type and a drain drift region (12) having a second, opposite, conductivity type; a gate dielectric layer (17) over the body region (11) and extending over a junction between the body region (11) and the drain drift region (12); a gate electrode (18) over the gate dielectric layer (17); a drain region (15) having the second conductivity type in the drain drift region (12), the drain region (15) having a dopant density greater than a dopant density of the drain drift region (12); a field relief dielectric layer (16) over the drain drift region (12), the field relief dielectric layer (16) extending from the gate dielectric layer (17) toward the drain region (15) and having a thickness greater than the gate dielectric layer (17); and a field plate (22) located over the field relief dielectric layer (16) and between the gate electrode (18) and the drain region (15), the field plate (22) spaced apart from the gate electrode (18); wherein the field plate (22) is not conductively connected to any other structure. Nakagawa specification ¶¶ 62-121. For purposes of this rejection, the phrase “not conductively connected” is interpreted such that capacitive arrangements are not considered to be conductively connected to any other structure.
Regarding claim 12, which depends from claim 10: Nakagawa discloses the field plate (22) extends between the drain region (15) and the gate [electrode] (18) by a distance that is at least twice a thickness of the field relief dielectric layer (16). See Nakagawa Figure 3. For purposes of this rejection, the distance is the collective distance of the field plate.
Regarding claim 16, which depends from claim 10: Nakagawa discloses the field plate (22) is electrically isolated from the gate electrode (18) and from the drain region (15). For purposes of this rejection,
Claims 3, 5, 11, and 15 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Nakagawa, with evidence from Choi, U.S. Pat. Pub. No. 2006/0145270.
Regarding claim 3, which depends from claim 1: Nakagawa is silent as to the presence of a silicide blocking layer covering an entire top side of the field plate (22). However, Nakagawa discloses first interlayer dielectric film (24) that is made of silicon oxide and overs an entire top side of the field plate (22). Nakagawa specification ¶ 91.
Choi, directed to similar subject matter, discloses a silicide blocking layer that may be formed of silicon oxide. Choi specification ¶ 14. Therefore, the first interlayer dielectric film (24), made of silicon oxide, is capable of being a silicide blocking layer.
Regarding claim 5, which depends from claim 1: Nakagawa discloses that the gate electrode (18) extends over the field relief dielectric layer (16) and is spaced apart from the field plate (22) by a first interlayer dielectric film (24) that is made of silicon oxide. Nakagawa is silent as to presence of a silicide blocking layer.
Choi, directed to similar subject matter, discloses a silicide blocking layer that may be formed of silicon oxide. Choi specification ¶ 14. Therefore, the first interlayer dielectric film (24), made of silicon oxide, is capable of being a silicide blocking layer.
Regarding claim 11, which depends from claim 10: Nakagawa discloses that the gate electrode (18) extends over the field relief dielectric layer (16) and is spaced apart from the field plate (22) by a first interlayer dielectric film (24) that is made of silicon oxide. Nakagawa is silent as to presence of a silicide blocking layer.
Choi, directed to similar subject matter, discloses a silicide blocking layer that may be formed of silicon oxide. Choi specification ¶ 14. Therefore, the first interlayer dielectric film (24), made of silicon oxide, is capable of being a silicide blocking layer.
Regarding claim 15, which depends from claim 10: Nakagawa is silent as to the presence of a silicide blocking layer covering an entire top side of the field plate (22). However, Nakagawa discloses first interlayer dielectric film (24) that is made of silicon oxide and overs an entire top side of the field plate (22). Nakagawa specification ¶ 91.
Choi, directed to similar subject matter, discloses a silicide blocking layer that may be formed of silicon oxide. Choi specification ¶ 14. Therefore, the first interlayer dielectric film (24), made of silicon oxide, is capable of being a silicide blocking layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa, and further in view of Shimizu, U.S. Pat. Pub. No. 2004/0232522, Figures 2 and 3.
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Regarding claim 6, which depends from claim 1: Nakagawa is silent as to whether the field plate includes polycrystalline silicon.
Shimizu Figures 2 and 3, directed to similar subject matter, disclose a gate electrode (9) and a field plate (12a-12c) that are located on isolation insulating film (10) and include polycrystalline silicon. Shimizu specification ¶ 73. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Nakagawa to include the Shimizu materials because the modification would have involved a selection of a known material based on its suitability for its intended use.
Claims 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Edwards, U.S. Pat. Pub. No. 2022/0149186, Figures 1A-1L, and further in view of Nakagawa.
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Regarding claim 17: Edwards Figures 1A-1L disclose a method of fabricating a semiconductor device (100), the method comprising: forming a body region (104) having a first conductivity type (p) in a semiconductor layer (104, 106) over a semiconductor substrate (102); forming a field relief dielectric layer (114) over the body region (104); forming a drain drift region (120) having a second, opposite, conductivity type (n) under the field relief dielectric layer (114); forming a gate dielectric layer (134) over the body region (104) and extending over a junction between the body region (104) and the drain drift region (120); forming a polysilicon layer (136) over the gate dielectric layer (134) and over the field relief dielectric layer (114); patterning the polysilicon layer (136) to form a gate electrode (140) over the gate dielectric layer (134) and a field plate (142) located over the field relief dielectric layer (114) and spaced apart from the gate electrode (140); implanting a source region (158) and a drain region (160) of the body region (104) with dopants of the second conductivity type (n); and forming electrically conductive contacts (172, 176, 178, 180) to the gate electrode (140) and to the source and drain regions (158, 160). Edwards specification ¶¶ 12-25. Edward does not disclose that the formation of the conductive contacts includes without forming any electrical connection to the field plate (142).
Nakagawa, directed to similar subject matter, discloses the formation of electrically conductive contacts (21, 32, 30; 23, 31, 29) to the source and drain regions (13, 15) without forming any electrical connection to the field plate (22). Nakagawa specification ¶¶ 78-80, 103, 104. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Edward to use the Nakagawa design because the Nakagawa design improves withstand voltage. Id. ¶¶ 24-26.
Regarding claim 18, which depends from claim 17: The combination discloses forming a metallization structure with contacts to the gate electrode (140), the source region (158), and the drain region (160) and no contact to the field plate (142) (as modified by Nakagawa).
Regarding claim 20, which depends from claim 18: Edwards discloses forming the field relief dielectric layer (114) includes performing a local oxidation of silicon (LOCOS) process. Edwards specification ¶ 14.
Allowable Subject Matter
Claims 2, 4, 8, 9, 13, 14, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For the record, the Office considered further modifying Edwards to include additional features from Nakagawa, and vice versa, but determined that Edwards was specifically designed for the drain-field plate electrical contact and that modifying Nakagawa beyond the modification in claims 17 and 18’s rejections to include those features (or modifying Nakagawa to include the Edwards features) would constitute impermissible hindsight. The floating field plate of Nakagawa is on a planar surface of the LOCOS layer, not on an edge portion facing the drain—to place the Nakagawa field plate in that location is impermissible hindsight.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 2: The claim has been found allowable because the prior art of record does not disclose “the field plate follows a path that has rounded corners with radii greater than a thickness of the field plate”, in combination with the remaining limitations of the claim.
With regard to claim 4: The claim has been found allowable because the prior art of record does not disclose “the field plate is located over a point at which the LOCOS layer ends at a top surface of the semiconductor layer”, in combination with the remaining limitations of the claim.
With regard to claim 8: The claim has been found allowable because the prior art of record does not disclose “the field plate extends over a tapered edge of the field relief dielectric layer”, in combination with the remaining limitations of the claim.
With regard to claim 9: The claim has been found allowable because the prior art of record does not disclose “a sidewall spacer on a sidewall of the field plate extends to the drain region”, in combination with the remaining limitations of the claim.
With regard to claim 13: The claim has been found allowable because the prior art of record does not disclose “the field plate extends over a tapered edge of the field relief dielectric layer”, in combination with the remaining limitations of the claim.
With regard to claim 14: The claim has been found allowable because the prior art of record does not disclose “a sidewall spacer that is located on a sidewall of the field plate and extends to the drain region”, in combination with the remaining limitations of the claim.
With regard to claim 19: The claim has been found allowable because the prior art of record does not disclose “forming a silicide blocking layer covering an entire top side of the field plate and extending between the field plate and the gate electrode”, in combination with the remaining limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m.
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/Victoria K. Hall/Primary Examiner, Art Unit 2897
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