DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 12/13/2025 is acknowledged.
Claim Objections
Claim 1 is objected to because of the following informalities: the spelling error “pluraity” in line 13 should be corrected. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 & 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 5 & 11 recite the limitation “a third pad”. It is unclear if the third pad is located on any of the chips or on the base layer. Correction/clarification is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,009,344 (Park). Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claim 1, Park teaches in claims 1 and 11 a semiconductor package comprising: a base layer comprising a first pad and a second pad; a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip, sequentially stacked over the base layer, wherein the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip, each includes a first chip identification pad and a second chip identification pad; a plurality of first wires sequentially connecting the first pad, the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip, wherein the pluraity of first wires are configured to supply power to the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip; and a second wire connecting the second pad to the second chip identification pad of the first semiconductor chip, wherein the second wire is configured to supply power to the first semiconductor chip.
Claims 2-6 are rejected for being dependent on claim 1.
Regarding claim 7, Park teaches in claims 6 and 11 a semiconductor package, comprising: a base layer comprising a first pad and a second pad; a first chip stack over the base layer, wherein the first chip stack includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip, sequentially stacked, wherein the first to fourth semiconductor chips of the first chip stack, each includes a first chip identification pad and a second chip identification pad; a second chip stack over the first chip stack, wherein the second chip stack includes a fifth semiconductor chip, a sixth semiconductor chip, a seventh semiconductor chip, and an eighth semiconductor chip, sequentially stacked, wherein the fifth to eighth semiconductor chips, each includes a first chip identification pad and a second chip identification pad; a plurality of first wires electrically connecting the first pad, the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, the second chip identification pad of the third semiconductor chip, the first chip identification pad of the fifth semiconductor chip, the first chip identification pad of the sixth semiconductor chip, the second chip identification pad of the seventh semiconductor chip; and a plurality of second wires electrically connecting the second pad, the second chip identification pad of the first semiconductor chip, and the second chip identification pad of the fifth semiconductor chip.
Claims 8-13 are rejected for being dependent on claim 7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 & 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak (US PUB. 2014/0252640) in view of KOOK (US PUB. 2011/0068449).
Regarding claim 1, Kwak teaches a semiconductor package comprising:
a base layer 11 comprising a first pad (one of the plurality of finger electrodes 17) and a second pad (the other of the plurality of finger electrodes 17 or one of the plurality of finger electrodes 18, see Fig. 1 & Fig. 5 );
a first semiconductor chip 51, a second semiconductor chip 52, a third semiconductor chip 53, and a fourth semiconductor chip 54, sequentially stacked over the base layer 11 (Fig. 5), wherein the first semiconductor chip 54, the second semiconductor chip 52, the third semiconductor chip 53, and the fourth semiconductor chip 54, each includes a first chip identification pad and a second chip identification pad (e.g. any of the numerous chip electrodes/pads shown in Fig. 1 & Fig. 5 on each chip in T1 and/or T2 can perform as a first chip identification pad and a second chip identification pad as it is understood that the chip pads include chip identification capability associated with each semiconductor chip); and
a second wire (one of the sequential bond wires in Fig. 1 & Fig. 5) connecting the second pad (one of the plurality of finger electrodes 17 or 18) to the second chip identification pad of the first semiconductor chip, wherein the second wire is configured to supply power to the first semiconductor chip (the wires are capable of supplying power).
While Kwak teaches a plurality of first wires (one of the sequential plurality of first bond wires in Fig. 1 & Fig. 5) sequentially connecting the first pad (one of finger electrodes 17), the first chip identification pad of the first semiconductor chip 51/31, the first chip identification pad of the second semiconductor chip 52/32, wherein the plurality of first wires are configured to supply power to the first semiconductor chip 51/31 (the wires are capable of supplying power), the second semiconductor chip 52/32, and the third semiconductor chip 53/33 (Fig.1 & Fig. 5); however, Kwak is silent on wherein the plurality of first wires is sequentially connecting the first pad and the second chip identification pad of the third semiconductor chip. Nonetheless, KOOK discloses wherein a plurality of first wires connect a first chip identification pad 220 of a first semiconductor chip 200, a first chip identification pad 320 of the second semiconductor chip 300, and the second chip identification pad of the third semiconductor chip 400 (see KOOK’s Fig. 1). This has the advantage of providing a variety of electrical connection options between the different pads of the three semiconductor chips within a chip stack. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Kwak with chip pad connection arrangement, as taught by KOOK, so as to provide a variety of chip pad connection arrangement/options.
Regarding claim 2, the combination of Kwak and KOOK teaches the semiconductor package according to claim 1, wherein the first chip identification pad of the third semiconductor chip and the first chip identification pad of the fourth semiconductor chip are not connected to the plurality of first wires nor the second wire (Kwak’s Fig. 1 & Fig. 5 & KOOK’s Fig. 1 & Fig. 4, and note that some of the chip pads on each chip are not connected to the plurality of first/second wires).
Regarding claim 3, the combination of Kwak and KOOK teaches the semiconductor package according to claim 1, wherein the second chip identification pad of the second semiconductor chip and the second chip identification pad of the fourth semiconductor chip are not connected to the plurality of first wires nor the second wire (Kwak’s Fig. 1 & Fig. 5 & KOOK’s Fig. 1 & Fig. 4, and note that some of the chip pads on each chip are not connected to the plurality of first/second wires).
Regarding claim 4, the combination of Kwak and KOOK teaches the semiconductor package according to claim 1, wherein: the first chip identification pads are aligned with each other in a first direction, and the second chip identification pads are aligned with each other in the first direction (see Kwak’s Fig. 1 & Fig. 5, and KOOK’s Fig. 1 & Fig. 4).
Regarding claim 5, the combination of Kwak and KOOK teaches the semiconductor package according to claim 1, further comprising: a third pad (e.g. one of the numerous electrodes/pads 17 or 18); and a plurality of third wires (one of the numerous wires in T1 or T2) sequentially connecting the third pad, a third chip identification pad of the first semiconductor chip, a third chip identification pad of the second semiconductor chip, a third chip identification pad of the third semiconductor chip, and a third chip identification pad of the fourth semiconductor chip, wherein the plurality of third wires are configured to supply power to the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip (the wires are capable of supplying power, see Kwak’s Fig. 1 & Fig. 5, and KOOK’s Fig. 1 & Fig. 4).
Regarding claim 6, the combination of Kwak and KOOK teaches the semiconductor package according to claim 5, wherein the third chip identification pads are aligned with each other in a first direction (see Kwak’s Fig. 1 & Fig. 5, and KOOK’s Fig. 1 & Fig. 4).
Regarding claim 7, Kwak teaches a semiconductor package, comprising:
a base layer 11 comprising a first pad (one of the plurality of finger electrodes 17) and a second pad (the other of the plurality of finger electrodes 17 or one of the plurality of finger electrodes 18, see Fig. 1 & Fig. 5 );
a first chip stack (51-54) over the base layer 11, wherein the first chip stack includes a first semiconductor chip 51, a second semiconductor chip 52, a third semiconductor chip53, and a fourth semiconductor chip 54, sequentially stacked, wherein the first to fourth semiconductor chips of the first chip stack, each includes a first chip identification pad and a second chip identification pad (e.g. any of the numerous chip electrodes/pads shown in Fig. 1 & Fig. 5 on each chip in T1 and/or T2 can perform as a first chip identification pad and a second chip identification pad as it is understood that the chip pads include chip identification capability associated with each semiconductor chip);
a second chip stack (55-58) over the first chip stack, wherein the second chip stack includes a fifth semiconductor chip 55, a sixth semiconductor chip 56, a seventh semiconductor chip 57, and an eighth semiconductor chip 58, sequentially stacked, wherein the fifth to eighth semiconductor chips, each includes a first chip identification pad and a second chip identification pad (e.g. any of the numerous chip electrodes/pads shown in Fig. 1 & Fig. 5 on each chip in T1 and/or T2 can perform as a first chip identification pad and a second chip identification pad as it is understood that the chip pads include chip identification capability associated with each semiconductor chip); and
a plurality of second wires (e.g. 21A & 21B) electrically connecting the second pad (one of the plurality of finger electrodes 17 or 18), the second chip identification pad of the first semiconductor chip 51, and the second chip identification pad of the fifth semiconductor chip 55 (Fig. 1 & Fig. 5).
While Kwak teaches a plurality of first wires (one of the sequential plurality of first bond wires in Fig. 1 & Fig. 5) electrically connecting the first pad (one of finger electrodes 17), the first chip identification pad of the first semiconductor chip 51/31, the first chip identification pad of the second semiconductor chip 52/32, the first chip identification pad of the fifth semiconductor chip, the first chip identification pad of the sixth semiconductor chip (Fig. 1 & Fig. 5); however, Kwak is silent on wherein the plurality of first wires is electrically connecting the first pad and the second chip identification pad of the third semiconductor chip and the second chip identification pad of the seventh semiconductor chip. Nonetheless, KOOK discloses wherein a plurality of first wires connect a first chip identification pad 220 of a first semiconductor chip 200, a first chip identification pad 320 of the second semiconductor chip 300, and the second chip identification pad of the third semiconductor chip 400 (see KOOK’s Fig. 1). Though KOOK teaches said arrangement of chip pad connections as shown in Fig. 1 with respect to one chip stack; however, one of the ordinary skill being one of the ordinary creativity can employ/duplicate KOOK’s chip pad connection layout in Kwak’s second stack (chips 55-58) as well. This has the advantage of providing a variety of electrical connection options between the different pads of the three semiconductor chips within a chip stack. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Kwak with chip pad connection arrangement, as taught by KOOK, so as to provide a variety of chip pad connection arrangement/options.
Regarding claim 8, the combination of Kwak and KOOK teaches the semiconductor package according to claim 7, wherein the first chip identification pad of the third semiconductor chip, the first chip identification pad of the fourth semiconductor chip, the first chip identification pad of the seventh semiconductor chip, and the first chip identification pad of the eighth semiconductor chip are not connected to the plurality of first wires nor the plurality of second wires (Kwak’s Fig. 1 & Fig. 5 & KOOK’s Fig. 1 & Fig. 4, and note that some of the chip pads on each chip are not connected to the plurality of first or second wires).
Regarding claim 9, the combination of Kwak and KOOK teaches the semiconductor package according to claim 7, wherein the second chip identification pad of the second semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the second chip identification pad of the eight semiconductor chip, are not connected to the plurality of first wires nor the plurality of second wires (Kwak’s Fig. 1 & Fig. 5 & KOOK’s Fig. 1 & Fig. 4, and note that some of the chip pads on each chip are not connected to the plurality of first or second wires).
Regarding claim 10, the combination of Kwak and KOOK teaches the semiconductor package according to claim 7, wherein: the first chip identification pads of the first to eighth semiconductor chips are aligned with each other in a first direction, and the second chip identification pads of first to eighth semiconductor chips are aligned with each other in the first direction (Kwak’s Fig. 1 & Fig. 5, and KOOK’s Fig. 1 & Fig. 4).
Regarding claim 11, the combination of Kwak and KOOK teaches the semiconductor package according to claim 7, further comprising: a third pad (e.g. one of the numerous electrodes/pads 17 or 18); and a plurality of third wires (one of the numerous wires in T1 or T2) electrically connecting the third pad, a third chip identification pad of the first semiconductor chip, a third chip identification pad of the second semiconductor chip, a third chip identification pad of the third semiconductor chip, and a third chip identification pad of the fourth semiconductor chip, wherein the plurality of third wires are configured to supply power to the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip (the wires are capable of supplying power, see Kwak’s Fig. 1 & Fig. 5, and KOOK’s Fig. 1 & Fig. 4).
Regarding claim 12, the combination of Kwak and KOOK teaches the semiconductor package according to claim 11, wherein a third chip identification pad of the fifth semiconductor chip, a third chip identification pad of the sixth semiconductor chip, a third chip identification pad of the seventh semiconductor chip, and a third chip identification pad of the eighth semiconductor chip are not connected to the plurality of first wires, the plurality of second wires, nor the plurality of third wires (Kwak’s Fig. 1 & Fig. 5 & KOOK’s Fig. 1 & Fig. 4, and note that some of the chip pads on each chip are not connected to the plurality of first, second or third wires).
Regarding claim 13, the combination of Kwak and KOOK teaches the semiconductor package according to claim 12, wherein the third chip identification pads of the first to eighth semiconductor chips are aligned with each other in a first direction (Kwak’s Fig. 1 & Fig. 5, and KOOK’s Fig. 1 & Fig. 4).
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818