DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 05/13/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Patent 12,009,344 (Park) has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-6, 7 & 10-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “wherein the first chip identification pad of the third semiconductor chip and the first chip identification pad of the fourth semiconductor chip are not connected to the plurality of first wires nor the second wire not to receive power, and wherein the second chip identification pad of the second semiconductor chip and the second chip identification pad of the fourth semiconductor chip are not connected to the plurality of first wires nor the second wire not to receive power” (note bolded portion). It is unclear what applicant intends to describe here. There is grammatical error that contributes towards the ambiguity. Correction is required.
Claims 4-6 are rejected for being dependent on claim 1.
Claim 7 recites the limitation “wherein the first chip identification pad of the third semiconductor chip, the first chip identification pad of the fourth semiconductor chip, the first chip identification pad of the seventh semiconductor chip, and the first chip identification pad of the eighth semiconductor chip are not connected to the plurality of first wires nor the plurality of second wires not to receive power, and wherein the second chip identification pad of the second semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the second chip identification pad of the eight semiconductor chip, are not connected to the plurality of first wires nor the plurality of second wires not to receive power. It is unclear what applicant intends to describe in said limitation. There is grammatical error that contributes towards the ambiguity. Correction is required.
Claims 10-13 are rejected for being dependent on claim 7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak (US PUB. 2014/0252640) in view of KOOK (US PUB. 2011/0068449).
Regarding claim 1, Kwak teaches a semiconductor package comprising:
a base layer 11 comprising a first pad (one of the plurality of finger electrodes 17) and a second pad (the other of the plurality of finger electrodes 17 or one of the plurality of finger electrodes 18, see Fig. 1 & Fig. 5 );
a first semiconductor chip 51, a second semiconductor chip 52, a third semiconductor chip 53, and a fourth semiconductor chip 54, sequentially stacked over the base layer 11 (Fig. 5), wherein the first semiconductor chip 54, the second semiconductor chip 52, the third semiconductor chip 53, and the fourth semiconductor chip 54, each includes a first chip identification pad and a second chip identification pad (e.g. any of the numerous chip electrodes/pads shown in Fig. 1 & Fig. 5 on each chip in T1 and/or T2 can perform as a first chip identification pad and a second chip identification pad as it is understood that the chip pads include chip identification capability associated with each semiconductor chip); and
a second wire (one of the sequential bond wires in Fig. 1 & Fig. 5) connecting the second pad (one of the plurality of finger electrodes 17 or 18) to the second chip identification pad of the first semiconductor chip, wherein the second wire is configured to supply power to the first semiconductor chip (the wires are capable of supplying power); and
wherein the first chip identification pad of the third semiconductor chip and the first chip identification pad of the fourth semiconductor chip are not connected to the plurality of first wires nor the second wire not to receive power (see Kwak’s Fig. 1 & Fig. 5, note that some of the chip pads on each chip are not connected to the plurality of first/second wires), and wherein the second chip identification pad of the second semiconductor chip and the second chip identification pad of the fourth semiconductor chip are not connected to the plurality of first wires nor the second wire not to receive power (see Kwak’s Fig. 1 & Fig. 5, note that some of the chip pads on each chip are not connected to the plurality of first/second wires).
While Kwak teaches a plurality of first wires (one of the sequential plurality of first bond wires in Fig. 1 & Fig. 5) sequentially connecting the first pad (one of finger electrodes 17), the first chip identification pad of the first semiconductor chip 51/31, the first chip identification pad of the second semiconductor chip 52/32, wherein the plurality of first wires are configured to supply power to the first semiconductor chip 51/31 (the wires are capable of supplying power), the second semiconductor chip 52/32, and the third semiconductor chip 53/33 (Fig.1 & Fig. 5); however, Kwak is silent on wherein the plurality of first wires is sequentially connecting the first pad and the second chip identification pad of the third semiconductor chip. Nonetheless, KOOK discloses wherein a plurality of first wires connect a first chip identification pad 220 of a first semiconductor chip 200, a first chip identification pad 320 of the second semiconductor chip 300, and the second chip identification pad of the third semiconductor chip 400 (see KOOK’s Fig. 1). This has the advantage of providing a variety of electrical connection options between the different pads of the three semiconductor chips within a chip stack. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Kwak with chip pad connection arrangement, as taught by KOOK, so as to provide a variety of chip pad connection arrangement/options.
Regarding claim 4, the combination of Kwak and KOOK teaches the semiconductor package according to claim 1, wherein: the first chip identification pads are aligned with each other in a first direction, and the second chip identification pads are aligned with each other in the first direction (see Kwak’s Fig. 1 & Fig. 5, and KOOK’s Fig. 1 & Fig. 4).
Regarding claim 5, the combination of Kwak and KOOK teaches the semiconductor package according to claim 1, further comprising: a third pad of the base layer (e.g. one of the numerous electrodes/pads 17 or 18); and a plurality of third wires (one of the numerous wires in T1 or T2) sequentially connecting the third pad, a third chip identification pad of the first semiconductor chip, a third chip identification pad of the second semiconductor chip, a third chip identification pad of the third semiconductor chip, and a third chip identification pad of the fourth semiconductor chip, wherein the plurality of third wires are configured to supply power to the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip (the wires are capable of supplying power, see Kwak’s Fig. 1 & Fig. 5, and KOOK’s Fig. 1 & Fig. 4).
Regarding claim 6, the combination of Kwak and KOOK teaches the semiconductor package according to claim 5, wherein the third chip identification pads are aligned with each other in a first direction (see Kwak’s Fig. 1 & Fig. 5, and KOOK’s Fig. 1 & Fig. 4).
Allowable Subject Matter
Claims 7 & 10-13 are allowable pending resolution of 112 issues.
Response to Arguments
With respect to claim 1, applicant's arguments filed 05/13/2026 have been fully considered but they are not persuasive. As best understood, the prior art teaches the ambiguous claim features as addressed in the rejection above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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