DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 4-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Applicant does not define what area represents the unit cross sectional area. Applicant discloses that adding fillers to a matrix represents a total cross-sectional area but does not define the area.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1,8,9,11,14-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al. (US-20220302081-A1; Hsu) .
Regarding claim 1, Hsu discloses a semiconductor package comprising: a die pad (Fig. 8, 122; ¶62); a semiconductor device (Fig. 8, 230; ¶62) that is arranged on the die pad, and that has a chip having a main surface (bottom), a main surface electrode (Fig. 8, 230b; ¶63) arranged on the main surface, a terminal electrode (Fig. 8, 230d; ¶63) arranged on the main surface electrode, and a sealing insulator (Fig. 8, 160; ¶79) including a first matrix resin and first fillers, and covering a periphery of the terminal electrode on the main surface such as to expose (to electrical contact) a part of the terminal electrode; and a package body (Fig. 8, 170m; ¶81) that includes a second matrix resin and second fillers, and that seals the die pad and the semiconductor device such as to cover the sealing insulator.
Regarding claim 8, Hsu discloses the semiconductor package according to Claim 1, wherein the first matrix resin (Fig. 8, 160; ¶79) consists of a thermosetting resin (epoxy resin), and the second matrix resin (Fig. 8, 170m; ¶81) consists of a thermosetting resin. (epoxy resin)
Regarding claim 9, Hsu discloses the semiconductor package according to Claim 1, wherein the first fillers (Fig. 8, 160; ¶79) are each composed of either or both of a spherical object and an indeterminate object, and the second fillers are each composed of either or both of a spherical object and an indeterminate object. (Fig. 8, 170m; ¶81)
Regarding claim 11, Hsu discloses the semiconductor package according to Claim 1, wherein the first fillers (Fig. 8, 160; ¶79) include at least one of ceramics, oxides, and nitrides, and the second fillers (Fig. 8, 170m; ¶81) include at least one of ceramics, oxides, and nitrides.
Regarding claim 14, Hsu discloses the semiconductor package according to Claim 1, wherein the terminal electrode (Fig. 8, 230d; ¶63) is thicker than the main surface electrode, (Fig. 8, 230b; ¶63) and the sealing insulator (Fig. 8, 160; ¶79) is thicker than the main surface electrode. (Fig. 8, 230b; ¶63)
Regarding claim 15, Hsu discloses the semiconductor package according to Claim 1, wherein the terminal electrode (Fig. 8, 230d; ¶63) is thicker than the chip (Fig. 8, 231; ¶66), and the sealing insulator (Fig. 8, 160; ¶79) is thicker than the chip.
Regarding claim 16, Hsu discloses the semiconductor package according to Claim 1, wherein the terminal electrode (Fig. 8, 230d; ¶63) has a terminal surface and a terminal side wall, and the sealing insulator (Fig. 8, 160; ¶79) has an insulating main surface that forms a single flat surface (against the sidewall) with the terminal surface, and covers the terminal side wall.
Regarding claim 17, Hsu discloses the semiconductor package according to Claim 1, wherein the chip (Fig. 8, 230; ¶62) has a side surface, and the sealing insulator (Fig. 8, 160; ¶79) has an insulating side wall that forms a single flat surface with the side surface.(clear from cited figure)
Regarding claim 18, Hsu discloses the semiconductor package according to Claim 1, wherein the semiconductor device (Fig. 8, 230; ¶62) further includes an insulating film (Fig. 8, 230c; ¶63) that partially covers the main surface electrode (Fig. 8, 230b; ¶63), and the sealing insulator (Fig. 8, 160; ¶79) has a portion that directly covers the insulating film.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2,3,10,12,13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US-20220302081-A1; Hsu) in view of Lee et al. (US-20070213476-A1; Lee).
Regarding claim 2, Hsu discloses the semiconductor package according to Claim 1, but is silent on wherein the first fillers are added into the first matrix resin at a first density, and the second fillers are added into the second matrix resin at a second density that is different from the first density.
Lee discloses filler density, size, and shape are result effective variables that directly influences a layer's strength, and moisture blocking characteristics. (¶29) It is also known in the art that these parameters directly effect a material’s coefficient of thermal expansion (CTE).
Therefore, before the effective filing date it would be obvious to one of ordinary skill in the art to adjust the relative filler density so that the second matrix adds more overall package protection by having a higher filler density than the first matrix.
Regarding claim 3, Hsu in view of Lee discloses the semiconductor package according to Claim 2, but is silent on wherein the second fillers are added into the second matrix resin at the second density that is higher than the first density.
However, Lee discloses filler density, size, and shape are result effective variables that directly influences a layer's strength, and moisture blocking characteristics. (¶29) It is also known in the art that these parameters directly effect a material’s coefficient of thermal expansion (CTE).
Therefore, before the effective filing date it would be obvious to one of ordinary skill in the art to adjust the relative filler density so that the second matrix adds more overall package protection by having a higher filler density than the first matrix.
Regarding claim 10, Hsu discloses the semiconductor package according to Claim 9, but is silent on wherein the first fillers are each composed of the spherical object, and the second fillers are each composed of the spherical object.
Lee discloses using a spherical filler in epoxy resin (¶30)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to choose the desirable filler shape for its suitability in effecting the protective characteristics of the matrix.
Regarding claim 12, Hsu discloses the semiconductor package according to Claim 1, but is silent on wherein the sealing insulator includes the first fillers that have different particle sizes, and the package body includes the second fillers that have different particle sizes.
It is known in the art the particle sizes vary in a matrix due to manufacturing processes. Also, sizes and shapes are result effective variables that directly affect the protective characteristics of the matrix material.
Lee discloses using particle fillers with an average diameter of about 5mu to about 30mu. This means that the particle sizes vary.(¶30)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to fillers of different sizes due to manufacturing processes in addition to providing more control over layer parameters when the sizes are varied intentionally.
Regarding claim 13, Hsu discloses the semiconductor package according to Claim 1, but is silent on wherein the first fillers each have a particle size of not less than 1 nm and not more than 100 μm, and the second fillers each have a particle size of not less than 1 nm and not more than 100 μm.
Lee discloses using particle fillers with an average diameter of about 5mu to about 30mu.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use the filler sizes of Lee for optimal CTE.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US-20220302081-A1; Hsu) in view of Roesner et al. (US-20170358494-A1; Roesner).
Regarding claim 19, Hsu discloses the semiconductor package according to Claim 1, but is silent on wherein the chip includes a monocrystal of a wide bandgap semiconductor.
Roesner discloses a chip (Fig. 2, 1; ¶43) analogous to chip layer 231 of Hsu comprising a monocrystalline wide bandgap semiconductor material (Fig. 2A, 15, 4H-SiC, 6H-SiC; ¶45)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a wide bandgap monocrystalline material for the benefit of providing higher breakdown electric fields.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US-20220302081-A1; Hsu) in view of Yow et al. (US-20150054099-A1; Yow).
Regarding claim 20, Hsu discloses the semiconductor package according to Claim 1, but is silent on further comprising: a lead terminal that is arranged at an interval from the die pad; and a conducting wire that is connected to the terminal electrode and the lead terminal, wherein the package body seals the die pad, the lead terminal, the semiconductor device, and the conducting wire such as to partially expose the lead terminal.
Yow discloses a lead terminal (Fig. 2, 206; ¶15) that is arranged at an interval from the MCU chip (Fig. 2, 204; ¶15) and associated pads and terminals; and a conducting wire (Fig. 2,214; ¶18) that is connected to the MCU, wherein a package body (Fig. 2, 216; ¶19) seals the MCU chip, and the conducting wire such as to partially expose the lead terminal. (so the wiring can have a space to connect)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to attach the package to a lead frame for package stability when coupling to a motherboard or PCB.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./ Examiner, Art Unit 2899
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