Prosecution Insights
Last updated: October 02, 2026
Application No. 18/650,795

EMBEDDED INDUCTOR MODULE AND PACKAGED SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Apr 30, 2024
Priority
Jun 20, 2023 — provisional 63/509,131
Examiner
NGUYEN, DUY T V
Art Unit
Tech Center
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
853 granted / 1081 resolved
+18.9% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
53 currently pending
Career history
1130
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
55.2%
+15.2% vs TC avg
§102
22.6%
-17.4% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1081 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions 1. Applicant’s election without traverse of Group I, claims 1-14 in the reply filed on 7/16/2026 is acknowledged. Further, Applicant's election with traverse of Group 1a, claims 1-8 in the reply filed on 7/16/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Specification 2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 3. Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Do et al. (US 2022/0310512) in view of Hou et al. (US 2020/0211959). Re claim 1, Do teaches, under BRI, Figs. 1A-c & 3A-K, [0034-0036, 0053, 0057 0077], a package apparatus comprising: -a multi-layer substrate (package dielectric 101, Fig. 1) having multiple substrate layers (dielectric laminate layers) between first and second opposing surfaces, electrical traces (102, 103) on or within at least one of the multiple substrate layers, a cavity (304, Fig. 3D) extending from the first surface through at least one of the substrate layers (dielectric laminate layers) into the multi-layer substrate (101) to define a cavity floor and cavity sidewalls extending from the cavity floor along the at least one of the substrate layers (laminate layers) to the first surface, at least one conductive terminal (106b) exposed on the cavity floor, an arrangement of terminals (103) on the first surface of the multi-layer substrate (101) being spaced laterally from the cavity (304), and at least one of the terminals (103) being coupled to at least one of the respective electrical traces (102, 103); and -an inductor module (105) including a conductor (windings 106a, b) embedded within a dielectric substrate and having inductor terminals (107, 108, 113), the inductor module (105) having first and second opposing surfaces spaced apart from each other by a side edge thereof, the second surface of the inductor module (105) sitting on the cavity floor (of 304) with the side edge thereof extending from the second surface to terminate at the first surface of the inductor module (105), and at least one of the inductor terminals (107, 108) being coupled to the at least one conductive terminal (106b) on the cavity floor (of 304). PNG media_image1.png 380 607 media_image1.png Greyscale Do does not explicitly teach a mold compound encapsulating the inductor module and at least a portion of the multi-layer substrate. Hou teaches, Fig. 1, [0015, 0016], a mold compound (130) encapsulating the inductor module (120, 125) and at least a portion of the multi-layer substrate (110). As taught by Hou, one of ordinary skill in the art would utilize & modify the above teaching into Do to obtain a mold compound as claimed, because mold compound is an essential element in a package, and it aids in enhancing protection to the formed package structure. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hou in combination Do due to above reason. Re claim 2, in combination cited above, Hou teaches wherein the multi-layer substrate is a leadframe [0028]. Re claim 3, in combination cited above, Hou teaches, Figs. 1-2, [0015], a die (102) having bond pads (103), in which the die is mounted to the first surface of the leadframe (110), in which the bond pads (103) are coupled to at least some of the terminals on the first surface of the leadframe (101), and the mold compound (130) also encapsulates the die (102). Re claim 4, Do teaches, Fig. 1, wherein the multi-layer substrate (101) [0034] comprises a multiple layers of an insulating buildup material (e.g., dielectric film laminate layers). Re claim 5, Do teaches wherein the dielectric substrate has a magnetic (e.g., iron, nickel, [0043]) permeability that is greater than the mold compound (see Hou’s teaching). Re claim 6, in combination cited above, Hou teaches, Fig. 1, [0015], wherein the mold compound (130) is a non-magnetic mold (e.g., not magnetic) and the dielectric substrate (125) is a magnetic mold compound. 4. Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Do as modified by Hou as applied to claim 1 above, and further in view of NG et al. (US 2023/0290735). The teachings of Do/Hou have been discussed above. Re claim 7, Do teaches, Figs. 1A-B, [0041-0043, 0047], wherein the conductor (106a, b) of the inductor module (105) is a multi-layer conductor comprising: a first wiring (106a) of a conductive material; a second wiring (106b) of the conductive material; and the dielectric substrate (101, 104a) encapsulates the first and second wirings (106a, b); and a central core (104b) of a magnetic mold compound within at least a portion of a central region (Fig. 1B). Do/Hou does not explicitly teach the first winding of a conductive material having a radially inner edge; the second winding of the conductive material spaced axially from and overlying the first winding, in which the second winding is coupled to the first winding through the dielectric substrate, the second winding has a radially inner edge coaxial with the radially inner edge of the first winding to define a central region extending coaxially through the first and second windings. NG teaches, Figs. 8-9, [0023, 0047, 0048], the first winding (11) of a conductive material having a radially inner edge (at center of 11); the second winding (10) of the conductive material spaced axially from and overlying the first winding, in which the second winding (10) is coupled to the first winding (11) through the dielectric substrate (21), the second winding (10) has a radially inner edge (at center of 10) coaxial with the radially inner edge of the first winding (11) to define a central region extending coaxially through the first and second windings (11, 10). As taught by NG, one of ordinary skill in the art would utilize & modify the above teaching to obtain first & second windings having radially inner edges as claimed, because it aids in achieving desired inductor within a package having improved EMI and inductance. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by NG in combination Do/Hou due to above reason. Re claim 8, in combination cited above, NG teaches, Fig. 8, wherein each of the first and second windings (11, 10) has a spiral shape surrounding the central region. Conclusion 5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kim et al. (US 2015/0130579, Fig. 1) discloses multi spiral inductor including first/second spirals. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/27/26
Read full office action

Prosecution Timeline

Apr 30, 2024
Application Filed
Aug 17, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+16.7%)
2y 8m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1081 resolved cases by this examiner. Grant probability derived from career allowance rate.

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