DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
No claim to an application for domestic benefit.
Foreign Priority
Receipt is acknowledged of certified copies of papers (i.e., application number 10-2023-0137157 filed in Korea on 10/13/2023) required by 37 CFR 1.55 electronically retrieved 06/04/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/30/2024 was filed before first Office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title or similar is suggested:
-- IMAGE SENSOR WITH BURIED CONDUCTIVE LINER INSIDE PIXEL ISOLATION REGION AND FABRICATION METHOD OF THE SAME --.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5 and 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2011/0181749 A1 to Yamada.
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Regarding independent claim 1, Yamada teaches of an image sensor (see title) comprising:
a plurality of pixels 2 (“pixels”; see Figure 1 and Figure 4; paragraph 0060);
a semiconductor substrate 35 (“semiconductor substrate”; Figure 17J; paragraph 0073) comprising a first surface (i.e., opposite side of lens 85; see Figure 9 with Figure 17J) and a second surface (same side as of lens 85; see Figure 9 with Figure 17J) opposing the first surface (i.e., opposite side of lens 85; see Figure 9 with Figure 17J);
a device isolation layer (i.e., parts of 44 and surrounding liners/barriers/electrodes; see Figure 5 with Figure 17J; paragraph 0075) provided in a trench 55 (“groove”; Figure 17J; paragraph 0078) penetrating through the first surface (i.e., opposite side of lens 85; see Figure 9 with Figure 17J) and the second surface (same side as of lens 85; see Figure 9 with Figure 17J) of the semiconductor substrate 35, and separating the plurality of pixels 2 from each other (refer to paragraph 0075); and
a microlens 85 (“lens”; Figure 9 with Figure 17J; paragraph 0092) provided on the second surface,
wherein the device isolation layer (as defined infra) comprises:
a buried insulating pattern 59 (“insulating layer”; Figure 17J; paragraph 0082) penetrating through (see Figure 17J) the first surface (i.e., side of 35 opposite lens, refer to Figure 9) and the second surface (i.e., side of 35 that has lens, refer to Figure 9);
an insulating liner 56 (“gate insulating film”; Figure 17J; paragraph 0078) between the buried insulating pattern 59 and the semiconductor substrate 35;
a conductive liner 33/331/332 (“transfer gate” / “vertical transfer gate electrode” / “horizontal transfer gate electrode”; Figure 17J; paragraphs 0079, 0099) between the insulating liner 56 and the buried insulating pattern 59; and
a buried conductive pattern 64/62 (“plug” / “wiring lines”; Figure 17J; paragraph 0082; they are buried in the semiconductor device below the lens inside layer 63) provided on (i.e., 62 is “on” 59 via 61) at least a portion of the buried insulating pattern 59 and contacting (i.e., directly contacting) the conductive liner (i.e., 64 directly touching 33/332).
Regarding claim 2, Yamada teaches wherein the buried conductive pattern 64 is in direct physical contact (see Figure 17J) with a side surface (i.e., upper side surface of 332) of the conductive liner 332.
Regarding claim 5, Yamada teaches wherein the plurality of pixels 2 are arranged in a matrix when viewed in plan view (see Figure 1 with Figure 4),
wherein the device isolation layer (as defined in claim 1 rejection supra) comprises:
side portions extending in a row direction and a column direction (see Figure 4; 44 extends in both directions); and
intersection portions (i.e., row and column intersecting of Figure 4 of region 44) provided at regions in which the side portions intersect each other (see Figure 4), and
wherein the buried conductive pattern 62/64 (see Figure 17J) is provided in any one or any combination of the side portions (see Figure 17J with Figure 4; part of 62 connected to 64 spans 44) and the intersection portions (see Figure 17J with Figure 4; 64 at least at the corners of the FD square are at the intersection regions).
Regarding claim 15, Yamada teaches wherein the buried conductive pattern 62/64 comprises any one or any combination of doped polysilicon, metal (see paragraph 0082; 62 is in a wiring layer 63 that necessarily contains some metal), a metal oxide, a conductive organic material, or a conductive inorganic material (see paragraph 0082; 64 is conductive semiconductor therefore a conductive inorganic material).
Regarding claim 16, Yamada teaches wherein the conductive liner 33 comprises any one or any combination of metal (see paragraph 0099), a metal oxide, or doped polysilicon.
Regarding claim 17, Yamada teaches wherein the buried insulating pattern 59 comprises any one or any combination of tonen silazene (TOSZ), undoped silicate glass (USG), borosilica glass (BSG), phosphosilaca glass (PSG), borophosphor silica glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), or ozone-tetraethyl orthosilicate (O3-TEOS), silicon oxide (see paragraph 0100: there is silicon oxide), silicon nitride, or silicon oxynitride.
Regarding independent claim 18, Yamada teaches of an image sensor (see title) comprising:
a plurality of pixels 2 arranged in a matrix (see Figures 1 and 4);
a semiconductor substrate 35 comprising a first surface (i.e., opposite lens 85 of Figure 9) and a second surface (i.e., same side of lens 85 of Figure 9) opposing the first surface (i.e., opposite lens 85 of Figure 9), wherein the second surface (i.e., same side of lens 85 of Figure 9) is provided as a light-incident surface (hence lens); and
a device isolation layer (i.e., parts of 44 and surrounding liners/barriers/electrodes; see Figure 5 with Figure 17J; paragraph 0075) provided within a trench 55 (“groove”; Figure 17J; paragraph 0078) penetrating through the first surface (i.e., opposite side of lens 85; see Figure 9 with Figure 17J) and the second surface (same side as of lens 85; see Figure 9 with Figure 17J) of the semiconductor substrate 35, and separating the plurality of pixels 2 from each other (refer to paragraph 0075);
wherein the device isolation layer (i.e., parts of 44 and surrounding liners/barriers/electrodes; see Figure 5 with Figure 17J; paragraph 0075) comprises side portions (see Figure 1 and Figure 4; there are rows and columns that intersect each other), extending in a row direction and a column direction (see Figure 4), and intersection portions (see Figure 4) provided at regions in which the side portions intersect each other (see Figure 4), and
wherein each of the intersection portions (as defined infra) comprises:
a buried insulating pattern 59 (“insulating layer”; Figure 17J; paragraph 0082) extending from(see Figure 17J) the first surface (i.e., side of 35 opposite lens, refer to Figure 9) to the second surface (i.e., side of 35 that has lens, refer to Figure 9);
an insulating liner 56 (“gate insulating film”; Figure 17J; paragraph 0078; at the intersection at least at the corners of the square FD in Figure 4) between the buried insulating pattern 59 and the semiconductor substrate 35;
a conductive liner 33/331/332 (“transfer gate” / “vertical transfer gate electrode” / “horizontal transfer gate electrode”; Figure 17J; paragraphs 0079, 0099; at the intersection at least at the corners of the square FD in Figure 4) between the insulating liner 56 and the buried insulating pattern 59; and
a buried conductive pattern 64/62 (“plug” / “wiring lines”; Figure 17J; paragraph 0082; they are buried in the semiconductor device below the lens inside layer 63; at the intersection at least at the corners of the square FD in Figure 4. Also refer to claim 5 rejection supra) provided on (i.e., 62 is “on” 59 via 61) the buried insulating pattern 59 and contacting (i.e., directly contacting) the conductive liner (i.e., 64 directly touching 332).
Regarding independent claim 19, Yamada teaches of an image sensor (see title) comprising:
a plurality of pixels 2 arranged in a matrix (see Figures 1 and 4);
a semiconductor substrate 35 comprising a first surface (i.e., opposite side of lens 85, Figure 9) and a second surface (i.e., same side of lens 85) opposing the first surface (i.e., opposite side of lens 85, Figure 9);
a device isolation layer (i.e., parts of 44 and surrounding liners/barriers/electrodes; see Figure 5 with Figure 17J; paragraph 0075) provided within a trench 55 (“groove”; Figure 17J; paragraph 0078) penetrating through the first surface (i.e., opposite side of lens 85; see Figure 9 with Figure 17J) and the second surface (same side as of lens 85; see Figure 9 with Figure 17J) of the semiconductor substrate 35 to separate the plurality of pixels 2 from each other (refer to paragraph 0075), and comprising side portions (see Figure 4: there are rows and columns of 44 that intersect each other) and intersection portions (see Figure 4), the side portions extending in a row direction and a column direction (see Figure 4), and the intersection portions being in regions in which the side portions intersect each other (see Figure 4 and middle cross section views throughout Figures); and
a microlens 85 (see Figure 9) provided on the second surface (i.e., same side as lens 85),
wherein the device isolation layer (as defined infra) comprises:
a buried insulating pattern 59 (“insulating layer”; Figure 17J; paragraph 0082) penetrating through (see Figure 17J) the first surface (i.e., side of 35 opposite lens, refer to Figure 9) and the second surface (i.e., side of 35 that has lens, refer to Figure 9);
an insulating liner 56 (“gate insulating film”; Figure 17J; paragraph 0078) between the buried insulating pattern 59 and the semiconductor substrate 35;
a conductive liner 33/331/332 (“transfer gate” / “vertical transfer gate electrode” / “horizontal transfer gate electrode”; Figure 17J; paragraphs 0079, 0099) between the insulating liner 56 and the buried insulating pattern 59; and
a buried conductive pattern 64/62 (“plug” / “wiring lines”; Figure 17J; paragraph 0082; they are buried in the semiconductor device below the lens inside layer 63) provided on (i.e., 62 is “on” 59 via 61) at least a portion of the buried insulating pattern 59 and contacting (i.e., directly contacting) the conductive liner (i.e., 64 directly touching 33/332), and
wherein the buried conductive pattern 62/64 (see Figure 17J) is provided in any one or any combination of the side portions (see Figure 17J with Figure 4; part of 62 connected to 64 spans 44) and the intersection portions (see Figure 17J with Figure 4; 64 at least at the corners of the FD square are at the intersection regions).
Allowable Subject Matter
Claims 3-4, 6-14 and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 3, wherein the conductive liner surrounds a periphery of each of the plurality of pixels and extends between two adjacent pixels, among the plurality of pixels, and wherein the buried conductive pattern is provided between the conductive liner of each of the two adjacent pixels to electrically and physically connect two separated conductive liners.
Dependent claim 4 contains allowable subject matter, because it depends on the allowable subject matter of claim 3.
Claims 6 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 6, wherein one of the side portions comprises a first region having a first width and a second region having a second width greater than the first width, and wherein the device isolation layer comprises: a first device isolation layer provided in the first region; a second device isolation layer provided in the second region; and a third device isolation layer provided in the intersection portions.
Dependent claims 7-14 contains allowable subject matter, because they depend on the allowable subject matter of claim 6.
Claims 20 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 20, wherein one of the side portions comprises a first region having a first width and a second region having a second width, greater than the first width, along a direction parallel to the first surface, wherein the device isolation layer comprises: a first device isolation layer provided in the first region; a second device isolation layer provided in the second region; and a third device isolation layer provided at the intersection portions, and wherein the third device isolation layer comprises the buried conductive pattern.
Conclusion
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20 June 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
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