Prosecution Insights
Last updated: July 17, 2026
Application No. 18/650,970

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Apr 30, 2024
Priority
Dec 01, 2021 — JP 2021-195180 +1 more
Examiner
FERNANDES, ERROL V
Art Unit
Tech Center
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
691 granted / 811 resolved
+25.2% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
15 currently pending
Career history
825
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
84.9%
+44.9% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 811 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 and 9-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otremba et al US 2018/0061745 A1 in view of Hirumuta et al. US 6,111,312. Regarding claims 1-17, Otremba discloses: A semiconductor device (Fig. 2) comprising: a semiconductor element (120); a first lead including a die pad portion (110) and a first terminal portion (150/250), the die pad portion including a first lead obverse surface (110a) that faces a first side in a thickness direction and on which the semiconductor element is mounted and a first lead reverse surface (110b) that faces a second side in the thickness direction; and a sealing resin (140) including a first resin surface (140a) facing the first side in the thickness direction, a second resin surface (140b) facing the second side in the thickness direction, and a third resin surface (140 on the side surface perpendicular to 140a and 140b) facing a first side in a first direction perpendicular to the thickness direction, the sealing resin covering the semiconductor element and a portion of the die pad portion, wherein the first lead reverse surface is exposed from the second resin surface (110b exposed from 140b). Otremba does not disclose: the first terminal portion includes a first portion extending outward from the third resin surface to the first side in the first direction, a second portion located on the first side in the thickness direction relative to the first portion and used for mounting, and a third portion interposed between the first portion and the second portion, and the second portion overlaps with the sealing resin as viewed in the thickness direction. Hirumuta discloses a publication from a similar field of endeavor in which: the first terminal portion (14) includes a first portion (15) extending outward from the third resin surface (side surface of 23) to the first side in the first direction, a second portion (16) located on the first side in the thickness direction relative to the first portion and used for mounting, and a third portion (vertical region of 14 connecting 15 and 16) interposed between the first portion and the second portion, and the second portion overlaps with the sealing resin as viewed in the thickness direction (Fig. 4). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the lead of Hirumuta as an alternative to that of Otremba to further reduce the overall size of the semiconductor device. (claim 2) Hirumuta; Fig. 4; 16. (claim 3) Hirumuta: Fig. 4; vertical region of 14 connecting 15 and 16. (claim 4) Otremba: Fig. 2; 110b. (claim 5) Hirumuta; Fig. 4; 24 where 16 is accommodated. (claim 6) Hirumuta; Fig. 4; 16 overlapping bottom recessed side of 13. (claim 9) Otremba: Fig. 2; a connecting member 210, a second lead (160, 260). (claim 10) Hirumuta; Fig. 4; resin 13 on left side with vertical region of 14 connecting 15 and 16. (claim 11) Hirumuta; Fig. 4; 16. (claim 12) Hirumuta: Fig. 4; vertical region of 14 connecting 15 and 16. (claim 13) Hirumuta; Fig. 4; 24 where 16 is accommodated. (claim 14) Hirumuta; Fig. 4; 16 overlapping bottom recessed side of 13. (claim 15) Hirumuta; Fig. 4. (claim 16) Hirumuta; Fig. 4; a groove 24. (claim 17) Hirumuta; Fig. 4; portion of 13 between two groove 24 regions. Claims 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otremba/Hirumuta, as applied to claim 1 above, in view of Hatasa et al. US 2019/0229040 A1. Regarding claims 7 and 8, Otremba/Hirumuta do not disclose: (claim 7) wherein the die pad portion is larger than the first portion of the first terminal portion in the thickness direction; and (claim 8) wherein one side of the first portion is flush with the first lead obverse surface. Hatasa discloses a publication from a similar field of endeavor in which: (claim 7) wherein the die pad portion is larger than the first portion of the first terminal portion in the thickness direction; and (claim 8) wherein one side of the first portion is flush with the first lead obverse surface (Fig. 1; 16). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the die pad portion configuration of Hatasa as a replacement for that of Otremba to provide support for the pad region by surrounding the peripheral region with the encapsulant, thereby increasing reliability. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Apr 30, 2024
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685220
MODULAR SYSTEMS IN PACKAGES, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS
3y 10m to grant Granted Jul 14, 2026
Patent 12677428
METAL INSULATOR METAL CAPACITOR (MIM CAPACITOR)
2y 10m to grant Granted Jul 07, 2026
Patent 12672530
ELECTRONIC PACKAGE
4y 2m to grant Granted Jun 30, 2026
Patent 12672575
SEMICONDUCTOR STRUCTURE AND METHOD FOR ARRANGING REDISTRIBUTION LAYER OF SEMICONDUCTOR DEVICE
2y 10m to grant Granted Jun 30, 2026
Patent 12672571
ELECTRONIC DEVICE
2y 6m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+11.0%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 811 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month