DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant’s Traverse of the Restriction Requirement
Applicant’s election with traverse of Group I in the reply filed on August 03, 2026, is acknowledged. Applicant’s request for reconsideration under 37 CFR1.143 has been fully considered.
The restriction requirement, mailed June 3, 2026, is hereby WITHDRAWN. Upon further consideration, as serious search and examination burden has not been shown as between the device claims of Group I and the method of making claim s of Group II. Claims 18-21 are directed to a method of forming the device recited in claims 1, 2, 3, and 10 respectively; the field of search and the prior art applicable to Group II are coextensive with those applicable to Group I. Restriction is therefore not proper. See MPEP 803.
Claims 1-21 are examined on the merits herein.
The Examiner notes, however, that Applicant’s traverse addressed only one of the two
processes identified in the restriction requirement. Applicant’s argument is directed to reversal of
the layer build order and doe not address the separately identified wafer bonding process, in
which the fil resistor and the overlying pad metal layer are formed and thereafter transferred to a
supporting substrate, such that the film resistor is disposed over the pad metal layer with respect
the resulting semiconductor layer. Withdrawal of the restriction requirement is not an
acquiescence in Applicant’s characterization of that process.
Information Disclosure Statement
The information disclosure statements filed on 04/30/2024 and 07/17/2025 have been acknowledged and signed copies of the PTO-1449 are attached herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a) and 1.84 for the following reasons:
1. FIG. 37 is referenced but does not exist. The Brief Description of the Drawings recited “FIGS. 3-36,” while the Detailed Description refers to “FIGS. 2-37” and “FIGS. 3-37” (See Current application PG Publication Par [0028]). Applicant is required either to add the missing figure or to correct the references in the specification.
2. Reference numeral 150 designates two distinct structures. Numeral 150 is used for the molded package structure in Fig. 1 (See, for example, Current application PG Publication Par [0012], [0027]) and for the radius of curvature of the turnaround in Fig. 1B (See Current application PG Publication Par [0024]). Each reference character must designate a single element throughout. See 37 CFR 1.84(p)(4).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action.
Specification
The disclosure is objected to because of the following informalities:
Reference numeral 101 has no antecedent basis in the drawings. It appears numeral 102 (semiconductor layer) was intended.
“the polyimide layer 190 has gaps” (See, for example, current application PG Pub Par [0051]), It appears numeral 130 was intended.
“using direct eye integration”, (See, for example, current application PG Pub Par [0053]). It appears “using direct die integration”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (USPN 6497824 B1, hereinafter “Chen”).
In regards to claim 1, Chen discloses (See, for example, Figs. 2A-2E, See also annotated Fig. 2E included below) an integrated circuit, comprising:
a multilevel metallization structure (40, 64) over a semiconductor layer (10),
the multilevel metallization structure (40, 64) having a dielectric layer (30);
a pad metal layer (40) on the dielectric layer (30) and including first (401) and second (402) resistor terminals (terminating the resistive path at the two spaced-apart locations) ; and
a resistor (60) connected between the first and second resistor terminals and including a resistive path in a resistive layer over the pad metal layer (40),
a first location of the resistive path connected to the first resistor terminal (40, one of the two spaced-apart locations) by a first vertical interconnect (62), and
a second location of the resistive path connected to the second resistor terminal (40, one of the two spaced-apart locations) by a second vertical interconnect (62).
In regards to claim 18, Chen discloses (See, for example, Figs. 2A-2E, See also annotated Fig. 2E attached below) a method of fabricating an electronic device, the method comprising:
forming a dielectric layer (30) in a multilevel metallization structure (40, 64) over a semiconductor layer (10);
forming a pad metal layer (40) on the dielectric layer (30) and including first (401) and second (402) resistor terminals; and
forming a film resistor (60) over the pad metal layer (40),
a first location of the film resistor (60) connected to the first resistor terminal (401) by a first vertical interconnect (62), and
a second location of the film resistor (60) connected to the second resistor terminal (402) by a second vertical interconnect (62).
In regards to claim 4, Chen discloses (See, for example, Figs. 2A-2E) wherein the resistive layer comprises silicon and chromium (See, for example, Col. 2 line 66 thru Col. 3 line 2).
Claim 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aggarwal et al. (US 2016/0218062 A1, hereinafter “Aggarwal”).
In regards to claim 16, Aggarwal discloses (See, for example, Figs. 1, 3) an integrated circuit, comprising:
a semiconductor layer (See Par [0021]); and
a multilevel metallization structure (See, Abstract/Par [0013]) over the semiconductor layer (See, Par [0021]),
the multilevel metallization structure having a film resistor (124),
a first resistor terminal (122), a second resistor terminal (122) that is spaced apart from the first resistor terminal (122), and
a dielectric seal structure (118/128) that encloses the film resistor (124),
wherein the film resistor (124) is located on a first sublayer (118) of the dielectric seal structure (118/128), and a second sublayer (128) of the dielectric seal structure (118/128) is on the film resistor (124).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Aggarwal.
In regards to claims 2, 5 and 19, Chen discloses all limitations of claims 1 and 18 above except that the resistive layer is located on a first sublayer of a dielectric seal structure, and a second sublayer of the dielectric seal structure is on the resistive layer (claim 2); the resistive layer comprises silicon, chromium and carbon (claim 5); and comprising enclosing the film resistor in a dielectric seal structure in the multilevel metallization structure (Claim 19).
Aggarwal discloses (See, for example, Fig. 1) the resistive layer (124) is located on a first sublayer (118) of a dielectric seal structure (118/128), and a second sublayer (128) of the dielectric seal structure (118/128) is on the resistive layer (124); the resistive layer (124) comprises silicon, chromium and carbon (See, for example, Par [0016]); and comprising enclosing the film resistor (124) in a dielectric seal structure (118/128) in the multilevel metallization structure (See, Par [0013]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Chen by Aggarwal because having the backside dielectric sublayer would help enhance electrical performance of the thin film resistor.
Claims 3 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Aggarwal as applied to claims 2 and 19 above, and further in view of Linewih et al. (US 2021/0098363 A1, hereinafter “Linewih”).
In regards to claims 3 and 20, Chen as modified above discloses all limitations of claims 2 and 19, and that the first and second sub layers may have similar composition (See, for example, Par [0017], Aggarwal), enclosing the film resistor (124, Aggarwal) , and forming a second sublayer (128, Aggarwal) over and contacting the film resistor (124, Aggarwal) except that that the first and second sublayers comprise silicon oxynitride (claim 3); and wherein enclosing the film resistor includes: forming a first silicon oxynitride layer over a silicon dioxide layer (; forming the film resistor over and contacting the first silicon oxynitride layer; and forming a second silicon oxynitride layer over and contacting the film resistor (claim 20).
Linewih while disclosing a thin film based passive device teaches (See, for example, Fig. 1) the sublayer 160 comprise silicon oxynitride (See Par [0028]); and wherein enclosing the film resistor includes: forming a first silicon oxynitride layer (160, Par [0028]) over a silicon dioxide layer (122, See for example, “TEOS, silicon oxide…”, Par [0027]); forming the film resistor (150) over and contacting the first silicon oxynitride layer (160).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Chen by Linewih because this would help provide high precision back-end resistor and improved integration of thin film based passive components in devices.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Aggarwal in view of Linewih.
In regards to claim 17, Aggarwal discloses all limitations of claim 16 and the first (118) and second (128) sub layers may have similar composition (See, for example, Par [0017]) except that the first sublayer of the dielectric seal structure includes silicon oxynitride, and the second sublayer of the dielectric seal structure includes silicon oxynitride.
Linewhi discloses (See, for example, Fig. 1) that the first sublayer (160) of the dielectric seal structure includes silicon oxynitride (See, Par [0028]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Chen by Linewih because this would help provide high precision back-end resistor and improved integration of thin film based passive components in devices.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Stewart et al. (US 2023/0154974 A1, hereinafter “Stewart”).
In regards to claim 7, Chen discloses all limitations of claim 1 except that the dielectric layer is a silicon nitride layer on a silicon oxynitride layer.
Stewart while disclosing an electronic device teaches (See, for example, Fig. 1) the dielectric layer (114/115) is a silicon nitride layer (115, See Par [0027]) on a silicon oxynitride layer (114, See Par [0027]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to form the dielectric layer of Chen on which the pad metal layer is disposed, as silicon nitride layer on a silicon oxynitride layer as taught by Stewart because this would help mitigate voltage breakdown beneath the overlying metal. This is also improving high voltage isolation capability and preventing low voltage failures.
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Karino (US 2023/0082803 A1, hereinafter “Karino”).
In regards to claims 10 and 12, Chen discloses all limitations of claim 1 above except that a protective overcoat over the resistive layer, the protective overcoat including an inorganic dielectric layer; and an organic dielectric layer over the protective overcoat, openings in the organic dielectric layer and the protective overcoat exposing the first and second resistor terminals (claim 10); further comprising a first bond wire connected to the first resistor terminal, and a second bond wire connected to the second resistor terminal (claim 12).
Karino while disclosing a semiconductor element teaches (See, for example, Figs. 2 and 3) a protective overcoat (71/72) over the resistive layer (5a, 5b), the protective overcoat (71/72) including an inorganic dielectric layer (71/72, “TEOS, Si3N4”, See Par [0056]); and an organic dielectric layer (73, “polyimide”, See Par [0056]) over the protective overcoat (71/72), openings (7a, 7b) in the organic dielectric layer and the protective overcoat exposing the first and second resistor terminals (5a, 5b); and further comprising a first bond wire connected to the first resistor terminal, and a second bond wire connected to the second resistor terminal (“The first external connection electrode 5a and the second external connection electrode 5b exposed to the first opening 7a and the second opening 7b of the passivation film 7 each serve as a pad region to which a bonding wire with a diameter of about 200 micrometers to 400 micrometers made of metal such as aluminum (Al) can be connected.”, See Par [0054]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide the Chen device with Karino’s oxide/nitride passivation films 71/72 covered by polyimide film 73 and opened at 7a/7b to expose the resistor terminals for bonding wires because this would help protect the underlying metallization from moisture and mechanical stress while providing pad regions of sufficient strength for wire bonding to external circuitry.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Aggarwal as applied to claim 19 above, and further in view of Karino.
In regards to claim 21, Chen as modified above discloses all limitations of claim 19 except that forming a protective overcoat over the dielectric seal structure.
Karino discloses (See, for example, Figs. 2 and 3) that forming a protective overcoat (73) over the dielectric seal structure (4, 71/72).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide the Chen device with Karino’s oxide/nitride passivation films 71/72 covered by polyimide film 73 and opened at 7a/7b to expose the resistor terminals for bonding wires because this would help protect the underlying metallization from moisture and mechanical stress while providing pad regions of sufficient strength for wire bonding to external circuitry.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Karino as applied to claim 12 above, and further in view of Nandakumar et al. (US 2022/0375856 A1, hereinafter “Nandakumar”).
In regards to claim 13, Chen as modified above discloses (See, for example, Figs. 2 and 3, Karino) multilevel metallization structure and the bond wires (See, for example, Par [0038]) except that a molded package structure that encloses the multilevel metallization structure and the bond wires.
Nandakumar while disclosing an integration scheme to build resistor teaches (See, for example, Fig. 24) a molded package structure (2400) that encloses the multilevel metallization structure (“The electronic device 100 includes multilevel metallization structure…”, See Par [0032]) and the bond wires (“conductive leads 2402”, See Par [0061]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to enclose the wire bonded die of the Chen modified by Karino device in a molded package structure as taught by Nandakumar because this would help protect the die and the wire bonds from mechanical damage and environmental contamination and to provide a standard package form factor for board-level assembly.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Zuo et al. (US 2014/0217550 A1, hereinafter “Zuo”). In regards to claim 14, Chen discloses all limitations of claim 1 above except that
the resistor includes a serpentine structure between the first and second locations.
Zuo while disclosing metal film resistor teaches (See, for example, Figs. 3 and 4) the resistor (340’) includes a serpentine structure (configuration shown in Fig. 4B in which the resistor has two ends and a middle part with a series of turns) between the first and second locations.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to configure Chen’s resistive path with the series of turns shown in Zuo’s Fig. 4B would help obtain a longer resistive path and thus higher resistance value within the same die area.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Zuo as applied to claim 14 above, and further in view of Karino.
In regards to claim 15, Chen as modified above discloses all limitations of claim 14
above except that the resistor includes a resistive layer turnaround that connects ends of
adjacent linear segments, and a pad metal layer turnaround connected to the resistive layer turnaround by vertical interconnects.
Karino discloses (See, for example, Fig. 2 and 3) the resistor (5c) includes a resistive layer turnaround that connects ends of adjacent linear segments (3a, 3b), and a pad metal layer (external connection electrodes 5a, 5b having a first resistive layer connection terminal connected to one end of first resistive layer 3a through contact region 6 and a second resistive layer connection terminal connected to one end of second resistive layer 3b through contact region 6d ) turnaround connected to the resistive layer turnaround by vertical interconnects (turn around formed in the terminal metal level, joined to two resistive layer segments through vertical contacts and carrying no external connection of its own).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide the Chen device with Karino’s oxide/nitride passivation films 71/72 covered by polyimide film 73 and opened at 7a/7b to expose the resistor terminals for bonding wires because this would help protect the underlying metallization from moisture and mechanical stress while providing pad regions of sufficient strength for wire bonding to external circuitry.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Tanaka (US 2023/0058805 A1, hereinafter “Tanaka”).
In regards to claim 6, Chen discloses all limitations of claim 1 above except that the pad metal layer is at least 15 μm above a top surface of the semiconductor layer.
Tanaka while disclosing electronic component teaches (See, for example, Fig. 1) the pad metal layer is at least 15 μm above a top surface of the semiconductor layer (having the maximum thicknesses disclosed for each layers intervening between the top surface (3) of the semiconductor layer (2) and the bottom surface of the pad layer (61, 62) will be above 15 µm, See Par [0065] ).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to select thicknesses at or near the upper ends of Tanaka’s disclosed ranges because Tanaka teaches that a high voltage may be applied to the first wiring while a low voltage is applied to the second, and a person of ordinary skill in the art would have selected greater insulating thicknesses in order to withstand that applied voltage without breakdown to the underlying substrate. Discovering the optimum or workable dimensional range to a workable value involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Karino as applied to claim 10 above, and further in view of Tanaka.
In regards to claim 11, Chen as modified above discloses all limitations of claim 10 except that the resistive layer is spaced apart from the semiconductor layer by a spacing distance that is greater than or equal to 10 μm.
Tanaka while disclosing electronic component teaches (See, for example, Fig. 1) the resistive layer is spaced apart from the semiconductor layer by a spacing distance that is greater than or equal to 10 μm (having the maximum thicknesses disclosed for each layers intervening between the top surface (3) of the semiconductor layer (2) and the bottom surface of the resistive layer will be above 10 µm, See Par [0065] ).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to select thicknesses at or near the upper ends of Tanaka’s disclosed ranges because Tanaka teaches that a high voltage may be applied to the first wiring while a low voltage is applied to the second, and a person of ordinary skill in the art would have selected greater insulating thicknesses in order to withstand that applied voltage without breakdown to the underlying substrate. Discovering the optimum or workable dimensional range to a workable value involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Tanaka.
In regards to claim 8, Chen discloses all limitations of claim 1 except that there is a gap in the dielectric layer between the first and second resistor terminals.
Tanaka discloses (See, for example, Fig. 1) that there is a gap (a gap occupied by 15b. Where a concave portion 15b which may partially overlap the first end portion 41a of the first lower wiring layer 41 (See Fig. 3). Additionally, referring to FIG. 4, the concave portion 15b may partially overlap the first end portion 42a of the second lower wiring layer 42. See Pars [0122] and [0123]) in the dielectric layer between the first (41) and second (42) resistor terminals.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide the Chen device with a gap filled by a separate insulating portion 15b of Tanaka because interrupting the continuous dielectric between the two voltage domains lengths that lateral leakage path and thereby raises the voltage the structure withstands before surface breakdown between the terminals.
In regards to claim 9, Chen as modified above discloses (See, Fig. 1, Tanaka) the resistive layer is spaced apart from the semiconductor layer by a spacing distance that is greater than or equal to 10.0 μm (having the maximum thicknesses disclosed for each layers intervening between the top surface (3) of the semiconductor layer (2) and the bottom surface of the resistive layer will be above 10 µm, See Par [0065] ).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to select thicknesses at or near the upper ends of Tanaka’s disclosed ranges because Tanaka teaches that a high voltage may be applied to the first wiring while a low voltage is applied to the second, and a person of ordinary skill in the art would have selected greater insulating thicknesses in order to withstand that applied voltage without breakdown to the underlying substrate. Discovering the optimum or workable dimensional range to a workable value involves only routine skill in the art. In re Aller, 105 USPQ 233.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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