Prosecution Insights
Last updated: October 02, 2026
Application No. 18/651,275

IMAGE SENSING DEVICE

Non-Final OA §102§103
Filed
Apr 30, 2024
Priority
Sep 05, 2023 — RE 10-2023-0117994
Examiner
MALEK, MALIHEH
Art Unit
Tech Center
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
490 granted / 615 resolved
+19.7% vs TC avg
Minimal +4% lift
Without
With
+3.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
21 currently pending
Career history
635
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
61.7%
+21.7% vs TC avg
§102
23.3%
-16.7% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 615 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraph of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1-3, 5-9, 12-13, 15-17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin et al. (Pub. No. US 2022/0406825 A1, herein Jin). Regarding claim 1, Jin discloses an image sensing device comprising: a semiconductor substrate including: a first pixel region “PR” (Jin: paragraph [0057]) configured to include at least one first photoelectric conversion region 110 (Jin: paragraph [0055]) that converts incident light into photocharge and at least one first floating diffusion region “FD” (Jin: paragraph [0038]) configured to store the photocharge generated by the at least one first photoelectric conversion region, a second pixel region “PR” (Jin: paragraph [0057]) located adjacent to the first pixel region in a first direction, and configured to include at least one second photoelectric conversion region 110 (Jin: paragraph [0055]) that converts incident light into photocharge and at least one second floating diffusion region “FD” (Jin: paragraph [0038]) that stores the photocharge generated by the at least one second photoelectric conversion region, and a first inter-pixel isolation structure “PIS” (Jin: paragraph [0060]) disposed between the first pixel region and the second pixel region; a first gate “PG” (Jin: paragraph [0077]) disposed over the semiconductor substrate and extending to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region; and a second gate “PG” (Jin: paragraph [0078]) disposed at one side of the first gate on the semiconductor substrate and extending to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region (Jin: Figs. 3, 4B, 6, 8A-8B, 9, 12-13B). Regarding claim 2, Jin discloses the image sensing device according to claim 1, wherein: each of the first gate and the second gate has a bar shape, and the first gate and the second gate are arranged parallel to each other (Jin: Figs. 3, 4B, 6, 8A-8B, 9, 12-13B and paragraphs [0071], [0088], [0176]). Regarding claim 3, Jin discloses the image sensing device according to claim 2, wherein: the first gate and the second gate have a same width (Jin: Figs. 3, 4B, 6, 8A-8B, 9, 12-13B and paragraphs [0071], [0088], Here, since each two adjacent PG gates are considered to be the first and second gates in the stated figures, they are having the same width.). Regarding claim 5, Jin discloses the image sensing device according to claim 1, wherein the first gate includes: a drive gate connected to the at least one first floating diffusion region and the at least one second floating diffusion region (Jin: paragraphs [0030]-[0031], [0068]). Regarding claim 6, Jin discloses the image sensing device according to claim 1, wherein the second gate includes: a reset gate disposed at one side of each of the first floating diffusion region and the second floating diffusion region, and configured to reset the first floating diffusion region and the second floating diffusion region based on a reset signal (Jin: paragraphs [0039], [0043]-[0044]). Regarding claim 7, Jin discloses the image sensing device according to claim 1, further comprising: a third gate disposed at an opposite side of the first gate, and configured to extend across the first pixel region, the first pixel isolation structure, and the second pixel region (Jin: Figs. 3, 4B, 6, 8A-8B, 9, 12-13B and the third PG from the four PGs shown in the figures). Regarding claim 8, Jin discloses the image sensing device according to claim 7, wherein: each of the first to third gates has a bar shape, and the first to third gates are arranged parallel to each other (Jin: Figs. 3, 8A, 9, 12). Regarding claim 9, Jin discloses the image sensing device according to claim 8, wherein: the first to third gates have a same width (Jin: Figs. 3, 8A, 9, 12). Regarding claim 12, Jin discloses the image sensing device according to claim 1, wherein the semiconductor substrate further includes: a third pixel region ([0029]-[0031]) disposed adjacent to the first pixel region in a second direction perpendicular to the first direction, and configured to include at least one third photoelectric conversion region that converts incident light into photocharge and at least one third floating diffusion region that stores the photocharge generated by the at least one third photoelectric conversion region; a fourth pixel region disposed adjacent to the third pixel region in the first direction, and configured to include at least one fourth photoelectric conversion region that converts incident light into photocharge and at least one fourth floating diffusion region that stores the photocharge generated by the at least one fourth photoelectric conversion region; and a second inter-pixel isolation structure disposed between the third pixel region and the fourth pixel region (Jin: Figs. 3, 4B, 6, 8A-8B, 9, 12-13B and paragraphs [0055]-[0057], [0077]-[0078]). Regarding claim 13, Jin discloses the image sensing device according to claim 12, further comprising: a third gate disposed on the semiconductor substrate and extending in a bar shape to cross the third pixel region, the second inter-pixel isolation structure, and the fourth pixel region; and a fourth gate disposed at one side of the third gate on the semiconductor substrate and extending in a bar shape to cross the third pixel region, the second inter-pixel isolation structure, and the fourth pixel region (Jin: Figs. 3, 4B, 6, 8A-8B, 9, 12-13B and paragraphs [0071], [0088], [0176]). Regarding claim 15, Jin discloses an image sensing device, comprising: a unit pixel group including a plurality of unit pixels “PR” (Jin: paragraph [0057]) that are disposed adjacent to each other in a first direction and a second direction perpendicular to the first direction, each unit pixel including at least one photoelectric conversion region 110 (Jin: paragraph [0055]) that generates photocharge through conversion of incident light and at least one floating diffusion region “FD” (Jin: paragraph [0038]) that stores the photocharge generated by the at least one photoelectric conversion region, wherein the unit pixel group includes a central portion, a left portion located at one side of the central portion, and a right portion located at another side opposite to the one side of the central portion, wherein each of the left portion and the right portion includes a plurality of first gates “PG” (Jin: paragraph [0078]) extending in a first direction to cross a plurality of unit pixels that is adjacent to each other in the first direction, and the central portion includes a plurality of second gates “PG” (Jin: paragraph [0078]) having an island shape and isolated from each other (Jin: Figs. 3, 4B, 6, 8A-8B, 9, 12-13B). Regarding claim 16, Jin discloses the image sensing device according to claim 15, wherein: each of the first gates has a bar shape, and the first gates are arranged parallel to each other (Jin: Figs. 3, 4B, 6, 8A-8B, 9, 12-13B and paragraphs [0071], [0088], [0176]). Regarding claim 17, Jin discloses the image sensing device according to claim 15, wherein the first gates include: a drive gate connected to the at least one floating diffusion region (Jin: paragraphs [0030]-[0031], [0068]); a reset gate disposed at one side of the drive gate and configured to reset the floating diffusion region based on a reset signal (Jin: paragraphs [0039], [0043]-[0044]); and a selection gate disposed at another side opposite to the one side of the drive gate and configured to output a pixel signal to an output terminal based on a row selection signal (Jin: paragraphs [0039], [0047]-[0048], [0051]). Regarding claim 20, Jin discloses the image sensing device according to claim 15, wherein the second gates include: a plurality of transfer gates configured to transmit the photocharge generated by the at least one photoelectric conversion region to the at least one floating diffusion region based on a transfer signal (Jin: paragraphs [0038], [0041], [0050]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 4, 10 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jin. Regarding claims 4, 10, 18 and 19, Jin does not specifically disclose the image sensing device having the first gate and the second gate with different widths from each other, or wherein the drive gate, the reset gate, and the selection gate are extended to have a same/different width. However, the gates may have the same bar-shaped width when uniformity, layout simplicity, or matching is desired, or different width when transistor-specific electrical performance or layout optimization is desired. The widths of the drive, reset and selection gates may be the same or different to independently optimize the electrical characteristics of the respective transistors, including drive current, reset speed, readout performance, parasitic capacitance, leakage, and layout area. Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Jin’s image sensor by employing the different geometry and width as a person of ordinary skill in the art has good reasons to pursue the known options within his or her technical grasp. Allowable Subject Matter Claims 11 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 11, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, wherein each of the first photoelectric conversion region and the second photoelectric conversion region includes: a first sub-photoelectric conversion region; and a second sub-photoelectric conversion region disposed at one side of the first sub-photoelectric conversion region in a direction in which the first and second gates are extended, and isolated from the first sub-photoelectric conversion region by an inner-pixel isolation structure. Regarding claim 13, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, a third gate disposed on the semiconductor substrate and extending in a bar shape to cross the third pixel region, the second inter-pixel isolation structure, and the fourth pixel region; and a fourth gate disposed at one side of the third gate on the semiconductor substrate and extending in a bar shape to cross the third pixel region, the second inter-pixel isolation structure, and the fourth pixel region. Regarding claim 14, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, further comprising: at least one first transfer gate disposed in the first pixel region between the second gate and the fourth gate, and configured to transmit the photocharge generated by the at least one first photoelectric conversion region to the at least one first floating diffusion region based on a transfer signal; at least one second transfer gate disposed in the second pixel region between the second gate and the fourth gate, and configured to transmit the photocharge generated by the at least one second photoelectric conversion region to the at least one second floating diffusion region based on a transfer signal; at least one third transfer gate disposed in the third pixel region between the second gate and the fourth gate, and configured to transmit the photocharge generated by the at least one third photoelectric conversion region to the at least one third floating diffusion region based on a transfer signal; and at least one fourth transfer gate disposed in the fourth pixel region between the second gate and the fourth gate, and configured to transmit the photocharge generated by the at least one fourth photoelectric conversion region to the at least one fourth floating diffusion region based on a transfer signal. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. August 22, 2026 /MALIHEH MALEK/Primary Examiner, Art Unit 2813
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Prosecution Timeline

Apr 30, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
83%
With Interview (+3.6%)
2y 10m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 615 resolved cases by this examiner. Grant probability derived from career allowance rate.

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