DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of device embodiment 1 as shown in fig. 1BI (claims 1-8, 10, and 11 readable thereon, claims 9, 12-20 withdrawn) in the reply filed on 8/3/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8, 10, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US PGPub 2020/0111905; hereinafter “Liu”).
Re claim 1: Liu teaches (figs. 1-3) a microelectronic device, comprising: a first doped semiconductor region (N+ source region 115; e.g. paragraph 17) and a second doped semiconductor region (N+ drain region 120; e.g. paragraph 17) extending into a semiconductor substrate (105,170,175,110; hereinafter “S”), the first (115) and (120) second doped semiconductor regions having a first conductivity type (N-type) and the semiconductor substrate (S) having (well 170 is a p-well; e.g. paragraph 20) an opposite second conductivity type (P-type); a semiconductor layer (110; e.g. paragraph 17) contacting the first doped semiconductor region (115) and the second doped semiconductor region (120); a first conductive layer (electrode 125; e.g. paragraph 18) extending between the first doped semiconductor region (115) and the second doped semiconductor region (120); a second conductive layer (electrode 127; e.g. paragraph 19) extending between the second doped semiconductor region (120) and the first conductive layer (125); and a dielectric layer (130) touching the semiconductor layer (110), the first conductive layer (125) and the second conductive layer (127).
Re claim 2: Liu teaches the microelectronic device as recited in Claim 1, further comprising a dielectric spacer (180 of both 125 and 127) between and touching the first and second conductive layers (125, 127).
Re claim 3: Liu teaches the microelectronic device as recited in Claim 2, wherein the semiconductor layer (110) is one of first (110A) and second (110B) semiconductor layers connected between the first doped semiconductor region (115) and the second doped semiconductor region (120), and the first and second conductive layers (125, 127), the dielectric layer (130), and the dielectric spacer (180) being between the first and second semiconductor layers (110A, 110B).
Re claim 8: Liu teaches the microelectronic device as recited in Claim 1, further comprising a gate trench (trench between 110A and 110B; hereinafter “T”) extending into the semiconductor substrate (S), the gate trench (T) filled by the first conductive layer (125 would be provided on sides of the channel fin of finfet devices).
Re claim 10: Liu teaches the microelectronic device as recited in Claim 3, further comprising an inner spacer (180 of 125 adjacent 115A) of a dielectric material contacting a source region (115) between the first and second semiconductor layers (110A, 110B) electrically isolating the first conductive layer (125) from the source region (115), and an inner spacer (180 of 127 adjacent 120A) of a dielectric material contacting a drain region (120) between the first and second semiconductor layers (110A, 110B), electrically isolating second conductive layer (127) from the drain region (120).
Re claim 11: Liu teaches the microelectronic device recited in Claim 1, wherein the semiconductor layer (110) has a thickness greater than 10 nm (D1 as shown in fig 3 is 30nm, therefore 110 has a thickness of approximately the same scale of about 30nm; e.g. paragraph 27).
Claim(s) 1, 2, 4-7, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (US PGPub 2020/0335623; hereinafter “Shin”).
Re claim 1: Shin teaches (e.g. fig. 4) a microelectronic device, comprising: a first doped semiconductor region (N+ source 112; e.g. paragraph 30) and a second doped semiconductor region (N+ drain 122; e.g. paragraph 30) extending into a semiconductor substrate (100), the first and second doped semiconductor regions (112, 122) having a first conductivity type (N-type) and the semiconductor substrate (p-type substrate 100; e.g. paragraph 32) having an opposite second conductivity type (P-type); a semiconductor layer (upper layer of 110, 120 which contacts 112 and 122; hereinafter “SL”) contacting the first doped semiconductor region (112) and the second doped semiconductor region (122); a first conductive layer (gate 152; e.g. paragraph 59) extending between the first doped semiconductor region (112) and the second doped semiconductor region (122); a second conductive layer (162) extending between the second doped semiconductor region (122) and the first conductive layer (152); and a dielectric layer (154a, 164) touching the semiconductor layer (SL), the first conductive layer (152) and the second conductive layer (162).
Re claim 2: Shin teaches the microelectronic device as recited in Claim 1, further comprising a dielectric spacer (156, 166) between and touching the first and second conductive layers (152, 162).
Re claim 4: Shin teaches the microelectronic device as recited in Claim 1, wherein the first doped semiconductor region is a source region (N+ source region 112; e.g. paragraph 30) and the second doped semiconductor region is a drain region (N+ drain region 122; e.g. paragraph 30), the source region (112) and the drain region (122) having a first average dopant concentration (N+), and further comprising a drain drift region (upper region of 120; e.g. paragraph 48; hereinafter “DDR”) having the first conductivity type (N-type) and a lower second dopant concentration (120 has a lower concentration of n-type dopants 112,122; e.g. paragraph 48) in the semiconductor layer (SL) and extending from the drain region (122) toward the source region (112), and a channel region (region of p-type region 110 has a channel that can be formed under gate 152; e.g. paragraph 40; hereinafter “CR”) having the second conductivity type (P-type) between the drain drift region (120) and the source region (112).
Re claim 5: Shin teaches the microelectronic device as recited in Claim 4, further comprising a well region (p-well 110; e.g. paragraph 40) having the second conductivity type (P-type) within the semiconductor layer (SL) and the semiconductor substrate (100), surrounding the source region (112), and extending from the source region (112) towards the drain region (120).
Re claim 6: Shin teaches the microelectronic device as recited in Claim 4, wherein the source region (112) extends into a trench (trench like the one in the instant application adjacent the STI 130) within the semiconductor substrate (100) and further comprising a body region (110) having the second conductivity type (P-type body region 110; e.g. paragraph 40) along sides and a bottom of the trench (trench for 130).
Re claim 7: Shin teaches the microelectronic device as recited in Claim 4, wherein the drain region (122) extends into a trench (trench for 130) within the semiconductor substrate (100) and further comprising a buffer region (120) having the first conductivity type (n-well 120) along sides and a bottom of the trench (trench for 130).
Re claim 11: Shin teaches the microelectronic device recited in Claim 1, wherein the semiconductor layer (SL) has a thickness greater than 10 nm (substrates are microns thick, so SL would have a thickness of at least 10nm).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US PGPub 2021/0184032 to Nidhi shows nanosheet LDMOS structures in general.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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