DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group III (claims 16-27) in the reply filed on 7/6/26 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0287744 “Yang”) in view of Lowrey (US 2012/0052651).
Regarding claim 16, Yang discloses an operating method of a semiconductor device, the operating method comprising:
performing a normal write operation (“At 605, the method may include performing a write operation on a memory cell to store a logic state at the memory cell” [0106]) to make a memory cell have a set state or a reset state (the logic state corresponding to a “set” or “reset” state [0033]);
determining required reliability of data stored in the memory cell (“detect that a condition [i.e. reliability in relation to bit error rate [0085]] is satisfied” [0027]);
in response to the determination (i.e. based at least in part on detecting the condition [0109]), a threshold voltage level of the memory cell (615, determine to refresh the memory cell based on detecting the condition, which modifies a threshold voltage level [0101+]); and
decreasing (i.e. reducing) the increased threshold voltage level of the memory cell (reducing increased threshold voltage of the memory cell [0111-0112], i.e. the increased threshold voltage level due to read operations [0059]) according to whether the memory cell has the set state or the reset state [0057-0059].
Yang does not expressly disclose increasing a threshold voltage level of the memory cell.
Lowry discloses increasing a threshold voltage level of the memory cell (increasing a threshold voltage using a lower voltage [0086]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is modifiable as taught by Lowry for the purpose of facilitating data accessing schemes by modulating threshold voltages of resistive memories [0086+ of Lowrey], to further optimize the threshold voltage which is common and well known in the art to secure the integrity of data storage.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0287744 “Yang”) in view of Lowrey (US 2012/0052651), and further in view of Tang (US 2022/0020413).
Regarding claim 17, Tang discloses the operating method of claim 16, wherein the performing of the normal write operation comprises: providing a first positive bias voltage to a selected bit line and providing a first negative bias voltage to a selected word line, to make the memory cell have the set state (fig. 10 [0104]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Tang for the purpose of facilitating data accessing schemes by maintaining programmed states of particular memory cells [0103 of Tang], which is common and well known in the art to secure the integrity of data storage.
Regarding claim 18, Tang discloses the operating method of claim 17, wherein the performing of the normal write operation further comprises: providing the first positive bias voltage to the selected word line and providing the first negative bias voltage to the selected bit line, to make the memory cell have the reset state (fig. 10 [0104]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Tang for the purpose of facilitating data accessing schemes by maintaining programmed states of particular memory cells [0103 of Tang], which is common and well known in the art to secure the integrity of data storage.
Claim(s) 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0287744 “Yang”) in view of Lowrey (US 2012/0052651), in view of Tang (US 2022/0020413), and further in view of Choi et al. (US 2014/0169101 “Choi”).
Regarding claim 19, Choi discloses the operating method of claim 18, wherein the determining of the required reliability of data comprises: determining whether a location of the memory cell is in a specific area [0069+].
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Choi for the purpose of compensating for disturbances based on memory cell conditions [0007+ of Choi], which is common and well known in the art to secure the integrity of data storage.
Regarding claim 20, Choi discloses the operating method of claim 19, wherein the specific area stores the data including firmware, or root data, or both [0091].
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Choi for the purpose of compensating for disturbances based on memory cell conditions [0007+ of Choi], which is common and well known in the art to secure the integrity of data storage.
Regarding claim 21, Choi discloses the operating method of claim 19, wherein the increasing of the threshold voltage level of the memory cell is performed when the location of the memory cell is in the specific area (fig. 7A, 7B, 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Choi for the purpose of compensating for disturbances based on memory cell conditions [0007+ of Choi], which is common and well known in the art to secure the integrity of data storage.
Claim(s) 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0287744 “Yang”) in view of Lowrey (US 2012/0052651), in view of Tang (US 2022/0020413), in view of Choi et al. (US 2014/0169101 “Choi”), and further in view of Nishikawa et al. (US 2019/0096487 “Nishikawa”).
Regarding claim 22, Nishikawa discloses the operating method of claim 21, wherein the increasing of the threshold voltage level of the memory cell is skipped when the location of the memory cell is in an area other than the specific area (fig. 6, 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Nishikawa for the purpose of improving performance speeds in a highly integrated device [0145 of Nishikawa], which is common and well known in the art to reduce latencies to facilitating data accessing schemes.
Regarding claim 23, Tang discloses the operating method of claim 18, wherein the increasing of the threshold voltage level of the memory cell comprises: applying a third positive bias voltage to one of the selected bit line and the selected word line for a set time interval; and applying a third negative bias voltage to the other line for the set time interval (fig. 10 [0104]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Tang for the purpose of facilitating data accessing schemes by maintaining programmed states of particular memory cells [0103 of Tang], which is common and well known in the art to secure the integrity of data storage.
Regarding claim 24, Tang discloses the operating method of claim 23, wherein the decreasing of the increased threshold voltage level of the memory cell comprises: applying a second positive bias voltage to the selected bit line; and applying a second negative bias voltage to the selected word line (fig. 10 [0104]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Tang for the purpose of facilitating data accessing schemes by maintaining programmed states of particular memory cells [0103 of Tang], which is common and well known in the art to secure the integrity of data storage.
Regarding claim 24, Tang discloses the operating method of claim 24, wherein a level of the second positive bias voltage is lower than that of the first positive bias voltage and higher than a level of the third positive bias voltage, and wherein a level of the second negative bias voltage is higher than that of the first negative bias voltage and is lower than that of the third negative bias voltage (fig. 10 [0104]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yang is further modifiable as taught by Tang for the purpose of facilitating data accessing schemes by maintaining programmed states of particular memory cells [0103 of Tang], which is common and well known in the art to secure the integrity of data storage.
Allowable Subject Matter
Claim(s) 26-27 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 26 (and dependent claim 27), the prior art fails to teach or suggest the claimed limitations, namely a level difference between the third positive bias voltage and the third negative bias voltage is smaller than a level of a minimum threshold voltage in a threshold voltage distribution of the first memory cells, and wherein a level difference between the second positive bias voltage and the second negative bias voltage is smaller than a level of a minimum threshold voltage in a threshold voltage distribution of the second memory cells.
The allowable claims are supported in at least of the instant application.
Conclusion
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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