DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 12-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kurata, WO2020/100947 (as cited by Applicant).
Regarding claim 1, Kurata teaches a semiconductor device comprising:
a chip having a main surface (wherein the main surface is the top portion of 12/21);
a recessed portion 102/115 formed in the main surface; and
a sealing insulator 93 that covers the main surface, and that has an anker portion positioned in the recessed portion (figure 10Q).
Regarding claims 2-4, Kurata teaches the sealing insulator includes a resin (sealing resin layer), and has the anker portion including a part of the resin, wherein the resin consists of a thermosetting resin [0102], and the sealing insulator includes fillers 97 that are added into the resin, and has the anker portion that includes a part of the resin and a part of the fillers (figure 7 with figure 10M).
Regarding claim 5, Kurata teaches the recessed portion is formed in a peripheral edge portion of the main surface (figure 10Q).
Regarding claims 6-7, Kurata teaches the chip has a side surface, and the recessed portion is formed at an interval from the side surface and the chip has a side surface, and the recessed portion is continuous with the side surface (figure 10Q).
Regarding claims 8-10, Kurata teaches a main surface insulating film 21 that covers the main surface such as to expose the recessed portion; wherein the anker portion is in contact with the chip inside the recessed portion, wherein the main surface insulating film has a wall portion that is continuous with a wall surface of the recessed portion, wherein the main surface insulating film covers the main surface at an interval from the recessed portion (figure 10Q).
Regarding claim 12, Kurata teaches comprising: a main surface electrode 22 or 55/56 that is arranged on the main surface at an interval from a peripheral edge of the main surface; wherein the recessed portion 103 is formed in a region between the peripheral edge 104 of the main surface and the main surface electrode 22 or 55/56, and the sealing insulator 93 covers a periphery of the main surface electrode (figure 10Q).
Regarding claim 13-14, Kurata teaches an insulating film 23 that partially covers the main surface electrode 22 or 55/56-on the sidewalls; wherein the sealing insulator 93 has a portion that covers the main surface electrode across the insulating film (figure 10Q), wherein the insulating film has any one of or both of an inorganic insulating film (silicon nitride, [0032]) or an organic insulating film(figure 10Q).
Regarding claim 15-16, Kurata teaches: a terminal electrode 70 that is arranged on the main surface electrode; wherein the sealing insulator covers a periphery of the terminal electrode such as to expose a part of the terminal electrode, wherein the terminal electrode is thicker than the main surface electrode, and the sealing insulator is thicker than the main surface electrode (figure 10Q).
Regarding claim 17, Kurata teaches the chip has a laminated structure including a substrate and an epitaxial layer [0019], and includes the main surface from which the epitaxial layer is exposed, and the recessed portion penetrates the epitaxial layer such as to expose the substrate and the epitaxial layer (figure 10Q and [0019]).
Regarding claim 18, Kurata teaches the chip includes a monocrystal of a wide bandgap semiconductor [0019].
Regarding claim 19, Kurata teaches a semiconductor device comprising:
a chip having a main surface (wherein the main surface is the top portion of substrate 12/21);
a main surface electrode 22 that is arranged on the main surface at an interval from a peripheral edge of the chip; and
a recessed portion 102/115 that is formed in a region between the peripheral edge of the chip and the main surface electrode at the main surface.
Regarding claim 20, Kurata teaches the chip has a laminated structure including a substrate and an epitaxial layer [0019], and includes the main surface from which the epitaxial layer is exposed, and the recessed portion penetrates the epitaxial layer such as to expose the substrate and the epitaxial layer (figure 10Q).
Claim(s) 1 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida, US Patent Application Publication 2020/0075735
Regarding claim 1, Yoshida teaches a semiconductor device comprising:
a chip 10 having a main surface 25;
a recessed portion 11a,11b111c formed in the main surface; and
a sealing insulator 12b that covers the main surface, and that has an anker portion positioned in the recessed portion (figure 12).
Regarding claim 11, Yoshida teaches a recess insulating film 12a that covers a wall surface of the recessed portion; wherein the anker portion is in contact with the recess insulating film inside the recessed portion (figure 12).
Conclusion
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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