Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
Applicant' s amendment dated 1/28/2026 in which claims 1, 2, 4 and 5 were amended has been entered of record. Currently, claims 1-6 are pending in light of the amendment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Shukh (Patent Application Publication 2014/0319634) in view of Chang (U.S. Patent Application 5,898,619).
Claim 1. Shukh discloses a configuration bit circuit for a programmable logic device including a phase change memory, the configuration bit circuit comprising: a first phase change memory (2MC1 Shukh Fig 12) and a second phase change memory connected in series with each other (1MC1 Shukh Fig 12) between a first power source (source providing power on 2WL) and a second power source (source providing power on 2WL) but is silent with respect to a transmission gate comprising an NMOS transistor and a PMOS transistor connected in parallel, and the transmission gate connected to a node between the first phase change memory and the second phase change memory in a first direction, wherein the transmission gate enables a bidirectional voltage application to program the first phase change memory or the second phase change memory to a high resistance state having a threshold voltage higher than an operating voltage of the configuration bit circuit.
Chang discloses a transmission gate with an N and P channel transistor in parallel coupled to memory cells enabling a bidirectional voltage application as a suitable replacement for a select gate for the purpose of allowing reads and write to occur without a significant voltage drop (Chang, Abstract).
Since Shukh and Chang are both from the same field of endeavor (accessing nonvolatile memory), the purpose disclosed by Chang would have been recognized in the pertinent art of Shukh.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the transmission gate taught by Chang in place of the transistors in the circuit taught by Shukh for the purposes of allowing reads and write to occur without a significant voltage drop.
Claim 4. A method of programming the configuration bit circuit for the programmable logic device including the phase change memory according to Claim 1, the method comprising: when a voltage applied to the transmission gate from first power source (source providing power on 2WL) or the second power source source (source providing power on 2WL) through the first phase change memory (2MC1 Shukh Fig 12) or the second phase change memory (1MC1 Shukh Fig 12) is referred to as a first polarity voltage and a voltage applied from the transmission gate (gate of pT) through the first phase change memory (2MC1 Shukh Fig 12) or the second phase change memory (1MC1 Shukh Fig 12) to the first power source (source providing power on 2WL) or the second power source (source providing power on 2WL) is referred to as a second polarity voltage, programming the first phase change memory or the second phase change memory to be in a first resistance state by the first polarity voltage (either logic 0 or 1); and programming the first phase change memory or the second phase change memory to be in a second resistance state by the second polarity voltage (either logic 1 or 0), wherein one of the first phase change memory and the second phase change memory is in the first resistance state and -a remaining one of the first phased change memory and the second phase change memory is in the second resistance state (0 and 1), and one of the first resistance state and the second resistance state refers to a low resistance state because the phase change memory is in a crystalline phase (logic 0 is low), and a remaining one of the first resistance state and the second resistance state refers to a high resistance state because the phase change memory is in an amorphous phase (logic 1 is high).
Claim 5. A method of operating the configuration bit circuit for the programmable logic device including the phase change memory according to Claim 1, wherein a voltage applied to the first power source (source providing power on 2WL) or the second power source (source providing power on 2WL) for an operation of the configuration bit circuit is lower than a threshold voltage when the first phase change memory or the second phase change memory is in a high resistance state (GND 0V is lower than a threshold voltage when the first phase change memory or the second phase change memory is in a high resistance state).
Claim 6. A programmable logic element including the configuration bit circuit according to Claim 1 (Memory 120 Fig 2 is a programmable logic element including the configuration bit circuit).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shukh (Patent Application Publication 2014/0319634), in view of Chang (U.S. Patent Application 5,898,619), further in view of Fuji (Patent Application Publication 2007/0171706).
Claim 2. Shukh and Chang disclose the configuration bit circuit according to Claim 1 but does not disclose wherein a composition of a phase change layer in the first phase change memory and the second phase change memory includes Ge, Sb, and Te.
Fuji discloses phase change memory of Ge, Sb, and Te for the purpose of producing transitions between an amorphous and crystalline phase (Fuji [0002]).
Since Shukh, Chang and Fuji are from the same field of endeavor (phase change memory), the purpose disclosed by Fuji would have been recognized in the pertinent art of Shukh and Chang.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the materials taught by Fuji for the memory taught by Shukh for the purposes of transitions between an amorphous and crystalline phase.
Claim 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Shukh (Patent Application Publication 2014/0319634), in view of Chang (U.S. Patent Application 5,898,619), further in view of Kobayashi (Patent Application Publication 2021/0083184).
Claim 2. Shukh and Chang disclose the configuration bit circuit according to Claim 1 but does not disclose wherein a composition of a phase change layer in the first phase change memory element and the second phase change memory element includes Ge, Sb, and Te.
Kobayashi discloses phase change memory of Ge, Sb, and Te for the purpose of producing transitions between an amorphous and crystalline phase (Fuji [0067]).
Since Shukh, Chang and Kobayashi are both from the same field of endeavor (phase change memory), the purpose disclosed by Shukh and Change would have been recognized in the pertinent art of Kobayashi.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the materials taught by Kobayashi for the memory taught by Shukh and Chang for the purposes of transitions between an amorphous and crystalline phase.
Claim 3. The configuration bit circuit according to Claim 2, wherein the composition of the phase change layer is Ge < 50 at%, Sb < 40 at%, and Te ≥ 50 at% at an atomic ratio (the ratio is 2:2:4, Ge < 50 at%, Sb < 40 at%, and Te ≥ 50 at%, Kobayashi [0067]).
Response to Arguments
Amended claims 1, 2, 4 and 5 are addressed in the 103 rejection above.
Applicant's arguments with respect to claims 1-6 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/Primary Examiner, Art Unit 2827
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