DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/651,909 filed May 1, 2024. Claims 1-9 are currently pending and have been considered below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Hayashi (Pre-Grant Publication 2012/0267633) in view of Yamazaki (US Patent 9,494,830).
Regarding claim 1-4, Hayashi discloses a semiconductor device comprising:
a gate electrode (Fig. 1a-2d, 11);
a gate insulating layer (13) above the gate electrode;
a metal oxide layer (15; Paragraph [0041]) containing aluminum as a main component above the gate insulating layer;
a semiconductor layer (19a; Paragraph [0050]) that is crystallized to from polycrystalline structure above the metal oxide layer;
a source electrode (27s/29s) and a drain electrode (27d/29d) contacting the oxide semiconductor layer from above the oxide semiconductor layer; and
an insulating layer (31) above the source electrode and the drain electrode.
Hayashi does not disclose an oxide semiconductor layer. However Yamazaki disclose a semiconductor device comprising:
A channel/oxide semiconductor layer (23) wherein the oxide semiconductor can be polycrystalline oxide semiconductor layer (Col. 12, Lines 23-35 & Col. 35, Line 42-Col. 36 Line 15).
Yamazaki also disclose a voltage between the source and drain could be 0.1V (Col. 17, Lines 18-31)
It would have been obvious to those having ordinary skill in the art at the time of invention to form the channel as an oxide semiconductor layer because it will have high resistance when no electric field is applied thereby reducing off-state current and will exhibit high carrier mobility (Col. 35, Line 65-Col. 36, Line 2). Further although neither reference explicitly disclose a linear mobility of the semiconductor device is larger than 20 cm2/Vs when (Vg - Vth) × Cox = 5 × 10-7 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer, it has been held when the structure recited in reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent and a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977) MPEP 2112.01 I. Therefore since the combination of Hayashi and Yamazaki meets all of the structural limitations of the claim, the structure would be able to meet the same functional properties such as a linear mobility larger than 20 cm2/Vs when (Vg - Vth) × Cox = 5 × 10-7 or applying a voltage of 0.1V across the source and drain. Likewise the characteristics/properties of dependent claims 2-4 would also be anticipated by the structure of Hayashi and Yamazaki.
Regarding claim 5, Hayashi discloses a semiconductor device comprising:
a gate electrode (Fig. 1a-2d, 11);
a gate insulating layer (13) above the gate electrode;
a metal oxide layer (15; Paragraph [0041]) containing aluminum as a main component above the gate insulating layer;
a semiconductor layer (19a; Paragraph [0050]) that is crystallized to from polycrystalline structure above the metal oxide layer;
a source electrode (27s/29s) and a drain electrode (27d/29d) contacting the oxide semiconductor layer from above the oxide semiconductor layer; and
an insulating layer (31) above the source electrode and the drain electrode.
Hayashi does not disclose an oxide semiconductor layer. However Yamazaki disclose a semiconductor device comprising:
A channel/oxide semiconductor layer (23) wherein the oxide semiconductor can be polycrystalline oxide semiconductor layer (Col. 12, Lines 23-35 & Col. 35, Line 42-Col. 36 Line 15).
Yamazaki also disclose a voltage between the source and drain could be 0.1V (Col. 17, Lines 18-31).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the channel as an oxide semiconductor layer because it will have high resistance when no electric field is applied thereby reducing off-state current and will exhibit high carrier mobility (Col. 35, Line 65-Col. 36, Line 2). Further although neither reference explicitly disclose a linear mobility of the semiconductor device is larger than 30 cm2/Vs when (Vg - Vth) × Cox = 1 × 10-6 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer, it has been held when the structure recited in reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent and a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977) MPEP 2112.01 I. Therefore since the combination of Hayashi and Yamazaki meets all of the structural limitations of the claim, the structure would be able to meet the same functional properties such as a linear mobility larger than 30 cm2/Vs when (Vg - Vth) × Cox = 1 × 10-6.
Regarding claim 6-9, Hayashi discloses a semiconductor device comprising:
a gate electrode (Fig. 1a-2d, 11);
a gate insulating layer (13) above the gate electrode;
a metal oxide layer (15; Paragraph [0041]) containing aluminum as a main component above the gate insulating layer;
a semiconductor layer (19a; Paragraph [0050]) that is crystallized to from polycrystalline structure above the metal oxide layer;
a source electrode (27s/29s) and a drain electrode (27d/29d) contacting the oxide semiconductor layer from above the oxide semiconductor layer; and
an insulating layer (31) above the source electrode and the drain electrode.
Hayashi does not disclose an oxide semiconductor layer. However Yamazaki disclose a semiconductor device comprising:
A channel/oxide semiconductor layer (23) wherein the oxide semiconductor can be polycrystalline oxide semiconductor layer (Col. 12, Lines 23-35 & Col. 35, Line 42-Col. 36 Line 15).
Yamazaki also disclose a voltage between the source and drain could be 0.1V (Col. 17, Lines 18-31)
It would have been obvious to those having ordinary skill in the art at the time of invention to form the channel as an oxide semiconductor layer because it will have high resistance when no electric field is applied thereby reducing off-state current and will exhibit high carrier mobility (Col. 35, Line 65-Col. 36, Line 2). Further although neither reference explicitly disclose a normalized linear mobility of the semiconductor device is larger than 3.0 when (Vg - Vth) × Cox = 5 × 10-7 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer, it has been held when the structure recited in reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent and a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977) MPEP 2112.01 I. Therefore since the combination of Hayashi and Yamazaki meets all of the structural limitations of the claim, the structure would be able to meet the same functional properties such as a normalized linear mobility larger than 3.0 when (Vg - Vth) × Cox = 5 × 10-7 or applying a voltage of 0.1V across the source and drain. Likewise the characteristics/properties of dependent claims 7-9 would also be anticipated by the structure of Hayashi and Yamazaki.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Morita (Pre-Grant Publication 2024/0161698) discloses a display device comprising an oxide semiconductor and metal oxide stacked over gate electrode wherein the oxide semiconductor has a high mobility.
Cao (Pre-Grant Publication 2014/0084282) discloses a thin film transistor comprising a stacked insulating layer in a first insulating layer and a second insulating layer wherein the second insulating layer is an oxygen rich material.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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