DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/1/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE WITH NANOLAMINATE ELECTRODES.
Response to Amendment
The Preliminary Amendment submitted 5/1/2024 to: 1. Amend the Claims is acknowledged.
Claims Status
Claims 1-20 are currently pending and being examined. Claims 21-30 have been canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-6, 8-9; 10-11, 13-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Popovici (US 2013/0155572 A1) in view of BRUNEAU et al (US 2022/0033966 A1, hereafter Bruneau).
Re claim 1, Popovici discloses in FIG. 7 (with references to FIGS. 1-2 and 5) a semiconductor device (electronic memory; [0015]) comprising:
a capacitor (MIM 45; [0070]) comprising:
a first electrode (BE as in FIG. 1; [0029] and [0070]);
a second electrode (TE as in FIG. 1; [0029] and [0070]); and
a dielectric layer (D; [0070]) between the first electrode (BE) and the second electrode (TE),
wherein at least one of the first electrode (BE) and the second electrode (TE) comprises a nanolaminate electrode (BE1/BE2 or TE1/TE2; [0070]),
wherein the nanolaminate electrode (BE1/BE2 or TE1/TE2; [0070]) comprises a first material layer (BE1 or TE1; [0070]) and a second material layer (BE2 or TE2; [0070]), the first material layer (BE1 or TE1) and the second material layer (BE2 or TE2) being alternately arranged (stacked BE1/BE2 or TE1/TE2),
wherein the first material layer (BE1 or TE1) comprises indium oxide (as in FIG. 2; [0035]),
wherein the second material layer (BE2 or TE2) comprises molybdenum oxide (MoO2 as in FIGS. 2 and 5; [0036] and [0055]).
Popovici fails to disclose wherein the nanolaminate electrode (BE1/BE2 or TE1/TE2) comprises a plurality of first material layers (BE1 or TE1) and a plurality of second material layers (BE2 or TE2), the plurality of first material layers and the plurality of second material layers being alternately arranged, wherein the plurality of first material layers comprises indium oxide (In2O3), wherein the plurality of second material layers comprises molybdenum oxide (MoOx), wherein each of the plurality of first material layers has a thickness between about 2 angstroms to about 6 angstroms, and wherein each of the plurality of second material layers comprises a monolayer of molybdenum oxide (MoOx).
However,
Bruneau discloses DRAM capacitor components comprising: a plurality of indium oxide (In2O3) and molybdenum oxide (MoO2) layers, each of a desired thickness and alternately arranged ([0114]; [0122] and [0124]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Popovici, through routine experimentation (MPEP § 2144.05), for first and second nanolaminate electrodes more than 6 nm thick, by using the indium oxide (In2O3) and molybdenum oxide (MoO2) layers of Bruneau, configured wherein the nanolaminate electrode (BE1/BE2 or TE1/TE2) comprises a plurality of first material layers (BE1 or TE1) and a plurality of second material layers (BE2 or TE2), the plurality of first material layers and the plurality of second material layers being alternately arranged, wherein the plurality of first material layers comprises indium oxide (In2O3), wherein the plurality of second material layers comprises molybdenum oxide (MoOx), wherein each of the plurality of first material layers has a thickness between about 2 angstroms to about 6 angstroms, and wherein each of the plurality of second material layers comprises a monolayer of molybdenum oxide (MoOx), the nanolaminate electrodes having lower resistivities due to reduced carbon and nitrogen contamination of the indium oxide (In2O3) layers (Bruneau; [0126]-[0127]).
Re claim 2, Popovici discloses the semiconductor device of claim 1, wherein the nanolaminate electrode (BE1/BE2 or TE1/TE2) has a thickness greater than 6 nanometers ([0035]-[0036] and [0054]-[0055]).
But, fails to explicitly disclose wherein the nanolaminate electrode (BE1/BE2 or TE1/TE2) has a thickness between about 10 nanometers to about 50 nanometers.
However, Bruneau’s disclosure of nanolaminate layers of desired thicknesses would include a thickness between about 10 nanometers to about 50 nanometers, and render these limitations obvious, as part of the lower resistivity reduced carbon and nitrogen contaminated nanolaminate electrodes discussed for claim 1.
Re claim 3, Popovici and Bruneau disclose the semiconductor device of claim 1.
But, do not explicitly disclose wherein the nanolaminate electrode has a work function between about 4.95 eV to about 5.05 eV.
However, the nanolaminate electrode of Popovici and Bruneau comprises a plurality of indium oxide (In2O3) and molybdenum oxide (MoO2) layers as part of the lower resistivity reduced carbon and nitrogen contaminated nanolaminate electrodes discussed for claim 1, which is substantially identical to the claimed nanolaminate electrode, and would be expected to have the same properties of having a work function between about 4.95 eV to about 5.05 eV, establishing a prima facie case of obvious (MPEP § 2111.01).
Re claims 5-6, Popovici discloses the semiconductor device of claim 1, wherein the dielectric layer (D) comprises a high-k dielectric metal oxide (SrTiO3 or TiO2; [0037]); and wherein the dielectric layer comprises titanium oxide (TiO2; [0037]).
Re claims 8-9, Popovici and Bruneau disclose the semiconductor device of claim 1.
But, fail to disclose wherein the capacitor has a first capacitance at a first frequency of about 1 kHz, and a second capacitance at a second frequency of about 1 MHz, the second capacitance being greater than 50 % of the first capacitance; and wherein the second capacitance is greater than 80 % of the first capacitance.
However, the structure of Popovici and Bruneau is capable of being forming with the requisite nanolaminate composition such that a substantially identical structure results, with the expected characteristics of wherein the capacitor has a first capacitance at a first frequency of about 1 kHz, and a second capacitance at a second frequency of about 1 MHz, the second capacitance being greater than 50 % of the first capacitance; and wherein the second capacitance is greater than 80 % of the first capacitance, establishing a prima facie case of obviousness (MPEP § 2111.01).
Re claim 10, Popovici discloses in FIG. 7 (with references to FIGS. 1-2 and 5) a semiconductor device (electronic memory; [0015]) comprising a capacitor (MIM 45; [0070]) which comprises:
a first electrode (BE as in FIG. 1; [0029] and [0070]);
a second electrode (TE as in FIG. 1; [0029] and [0070]); and
a dielectric layer (D; [0070]) between the first electrode (BE) and the second electrode (TE),
wherein at least one of the first electrode (BE) and the second electrode (TE) comprises a nanolaminate electrode (BE1/BE2 or TE1/TE2; [0070]),
wherein the nanolaminate electrode (BE1/BE2 or TE1/TE2; [0070]) comprises:
a first material layer (BE1 or TE1; [0070]) comprising indium oxide (as in FIG. 2; [0035]) and;
a second material layer (BE2 or TE2; [0070]), alternately arranged (stacked BE1/BE2 or TE1/TE2) on the first material layer (BE1 or TE1), the second material layer (BE2 or TE2) comprises molybdenum oxide (MoO2 as in FIGS. 2 and 5; [0036] and [0055]).
Popovici fails to disclose wherein the nanolaminate electrode comprises: a plurality of first material layers comprising indium oxide (In2O3); and a plurality of second material layers respectively arranged between two adjacent first material layers of the plurality of first material layers, each of the plurality of second material layers comprising a monolayer of molybdenum oxide (MoOx), and wherein the nanolaminate electrode has a work function between about 4.95 eV to about 5.05 eV.
However, Bruneau renders these limitations obvious for nanolaminate electrodes, wherein the nanolaminate electrodes would have a work function between about 4.95 eV to about 5.05 eV, and lower resistivities due to reduced carbon and nitrogen contamination of the indium oxide (In2O3) layers as discussed for claims 1 and 3.
Re claim 11, Popovici and Bruneau disclose the semiconductor device of claim 10, wherein each of the plurality of first material layers has a thickness of about 2 angstroms to about 6 angstroms, and wherein the nanolaminate electrode has a thickness between about 10 nanometers to about 50 nanometers (see claims 1-2).
Re claims 13-14, Popovici discloses the semiconductor device of claim 10, wherein the dielectric layer comprises a high-k dielectric metal oxide (see claim 5); and wherein the dielectric layer comprises titanium oxide (TiO2; see claim 6).
Re claim 16, Popovici and Bruneau disclose the semiconductor device of claim 10, wherein the capacitor has a first capacitance at a first frequency of about 1 kHz, and a second capacitance at a second frequency of about 1 MHz, the second capacitance being greater than 50 % of the first capacitance (see claim 8).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nam et al (US 2006/0186452 A1, hereafter Nam) and Popovici (US 2013/0155572 A1) in view of BRUNEAU et al (US 2022/0033966 A1, hereafter Bruneau).
Re claim 17, Nam discloses in FIG. 7 (with references to FIGS. 1-6) a semiconductor device (capacitor) comprising;
a substrate (100; [0021]);
a contact structure (115; [0022]) on the substrate (100);
a lower electrode (140a; [0021]) on the contact structure (115), having a cylinder shape ([0021]);
a dielectric layer (150; [0021]) on the lower electrode (140a); and
an upper electrode (190; [0021]) on the dielectric layer (150).
Nam fails to disclose the lower electrode (140a) comprising a first nanolaminate electrode; and wherein the first nanolaminate electrode comprises: a plurality of first material layers comprising indium oxide (In2O3); and a plurality of second material layers respectively arranged between two adjacent first material layers of the plurality of first material layers, each of the plurality of second material layers comprising a monolayer of molybdenum oxide (MoOx), and wherein the first nanolaminate electrode has a work function between about 4.95 eV to about 5.05 eV.
However, Popovici and Bruneau would render these limitations by using their nanolaminate electrodes as substitutional equivalents (MPEP 2144.06) for providing capacitor electrodes, for electronic DRAM memories (Popovici and Bruneau), the lower electrode (140a) comprising a first nanolaminate electrode; and wherein the first nanolaminate electrode comprises: a plurality of first material layers comprising indium oxide (In2O3); and a plurality of second material layers respectively arranged between two adjacent first material layers of the plurality of first material layers, each of the plurality of second material layers comprising a monolayer of molybdenum oxide (MoOx), wherein the nanolaminate electrodes would have a work function between about 4.95 eV to about 5.05 eV, and lower resistivities due to reduced carbon and nitrogen contamination of the indium oxide (In2O3) layers as discussed for claims 1 and 3.
Re claim 18, Nam discloses the semiconductor device of claim 17, wherein the dielectric layer (150) comprises titanium oxide (TiO2; [0029]).
Re claim 19, Nam discloses the semiconductor device of claim 17.
But, fails to disclose wherein each of the plurality of first material layers has a thickness between about 2 angstroms to about 6 angstroms, and wherein the first nanolaminate electrode has a thickness between about 10 nanometers to about 50 nanometers.
However, Popovici and Bruneau disclose pluralities of first layers and nanolaminate layers of desired thicknesses, wherein it would be obvious for each of the plurality of first material layers has a thickness between about 2 angstroms to about 6 angstroms, and wherein the first nanolaminate electrode has a thickness between about 10 nanometers to about 50 nanometers, as part of the lower resistivity reduced carbon and nitrogen contaminated nanolaminate electrodes discussed for claims 1-2.
Re claim 20, Nam discloses the semiconductor device of claim 17, wherein the upper electrode (190) comprises a laminate electrode (160/170/180; [0021]).
But, fails to disclose wherein the upper electrode (190) comprises a second nanolaminate electrode, wherein the second nanolaminate electrode comprises: a plurality of third material layers comprising indium oxide (In2O3); and a plurality of fourth material layers respectively arranged between two adjacent third material layers of the plurality of third material layers, each of the plurality of fourth material layers comprising a monolayer of molybdenum oxide (MoOx), and wherein the second nanolaminate electrode has a work function between about 4.95 eV to about 5.05 eV.
However, Popovici and Bruneau would render these limitations by using their nanolaminate electrodes as substitutional equivalents (MPEP 2144.06) for providing capacitor electrodes, for electronic DRAM memories (Popovici and Bruneau), the upper electrode (190) comprising a second nanolaminate electrode, wherein the second nanolaminate electrode comprises: a plurality of third material layers comprising indium oxide (In2O3); and a plurality of fourth material layers respectively arranged between two adjacent third material layers of the plurality of third material layers, each of the plurality of fourth material layers comprising a monolayer of molybdenum oxide (MoOx), wherein the nanolaminate electrodes would have a work function between about 4.95 eV to about 5.05 eV, and lower resistivities due to reduced carbon and nitrogen contamination of the indium oxide (In2O3) layers as discussed for claims 1 and 3.
Claims 4, 7; 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Popovici and Bruneau as applied to claims 1; and 10 above, and further in view of Chang et al (US 2021/0126091 A1, hereafter Chang).
Re claims 4; and 12, Popovici and Bruneau disclose the semiconductor device of claims 1; and 10.
But, fail to discloses wherein, in an X-ray diffraction analysis result, the nanolaminate electrode exhibits a first peak derived from an indium oxide (222) plane having a cubic structure at 30.48 + 0.02° and a second peak derived from an indium oxide (400) plane at 35.43 ± 0.02°.
However, the structure of Popovici and Bruneau is capable of being forming with the requisite nanolaminate composition such that a substantially identical structure results, with the expected characteristics of wherein, in an X-ray diffraction analysis result, the nanolaminate electrode exhibits a first peak derived from an indium oxide (222) plane having a cubic structure at 30.48 + 0.02° and a second peak derived from an indium oxide (400) plane at 35.43 ± 0.02°, establishing a prima facie case of obviousness (MPEP § 2111.01).
Alternatively, Chang discloses in FIG. 8A alternating In2O3/MoO3 layers where the In2O3 layers have the known peaks from the (222) and (400) planes at about 30-31° and 35-36°, respectively ([0016]; [0071] and [0073]-[0074]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Popovici and Bruneau by using another form of molybdenum oxide (e.g. MoO3) for the nanolaminate electrode(s) where the In2O3 layers still have the known peaks from the (222) and (400) planes, with less residual strain (Chang; [0073]) and high electrical performance (Chang; [0029]).
Re claims 7; and 15, Popovici and Bruneau disclose the semiconductor device of claims 1; and 10.
But, fail to disclose wherein the nanolaminate electrode comprises a surface roughness of about 1 nm or less.
However, the structure of Popovici and Bruneau is capable of being forming with the requisite nanolaminate composition such that a substantially identical structure results, with the expected characteristics of wherein the nanolaminate electrode comprises a surface roughness of about 1 nm or less.
Alternatively, Chang discloses in FIG. 7 where In2O3/MoO3 bi-layers comprise a surface roughness of about 1 nm or less (0.5 nm or less; [0036] and [0070]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Popovici and Bruneau by using another form of molybdenum oxide (e.g. MoO3) for the nanolaminate electrode(s) where the In2O3 layer(s) and the MoO3 layer(s) are of near optimal quality for forming nanolaminate electrodes with less residual strain (Chang; [0073]) and high electrical performance (Chang; [0029]) as discussed for claims 4; and 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US-11233118-B2 discloses bi-layer conductive metal oxide electrodes; US-20090269880-A1 discloses well-known X-ray peaks from In2O3 layers; and US-20020123216-A1 discloses capacitors with cylindrical bottom electrode, all without be able to be used for satisfying, alone or in combination, the limitations of at least claims 1; 10; and 17.
One current trend in the materials for capacitors used in memory devices (e.eg. DRAM devices) is directed to avoiding leakage current increase as the size of the capacitors decrease, which can be accomplished by minimizing dielectric loss of the lower capacitor electrode due to dielectric relaxation, which lowers capacitance at higher frequencies.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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