DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-12, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hoerold (US 2008/0120586 A1) in view of You et al. (US 2023/0142050 A1).
Regarding claim 1, Hoerold discloses a method of forming a back-end-of-line (BEOL) region of an integrated circuit device, the method comprising (see ¶¶ [0033], [0058]-[0060]):
adding dummy metal lines to the non-full-track standard cell (Figs. 2-7; ref 250 “dummy shapes”);
performing metal patterning based on the full-track standard cell (Fig. 3, 5, 7; ¶ [0033]);
removing the dummy metal lines after performing the metal patterning (claim 2, “removing dummy shapes”; ¶ [0059] “removing metal wire”); and
forming top vias after removing the dummy metal lines (claim 6 “adding a via; ¶¶ [0058]-[0060].
While Hoerold teaches dummy metal shapes, it does not explicitly disclosed converting a non-full-track standard cell designed for the BEOL region to a full-track standard cell.
You teaches a method making an integrated circuit where adding dummy/filler features to regularize layout usage and fill unused routing space. In particular, You teaches forming an additional pattern between adjacent patterns when spacing exceeds a reference value, including a dummy pattern and/or extension pattern formed in empty track space to satisfy tip-to-tip spacing requirements and achieve a full-track structure. (See, e.g., ¶¶ [0006]–[0008], [0037]–[0044], [0108]–[0118], [0124]–[0127]).
It would have been obvious to modify the BEOL layout of Hoerold to include dummy metal lines or filler features, thereby yielding a more regular, track-filled layout as taught by You. The claimed “non-full-track” to “full-track” conversion is merely an articulation of that obvious modification.
Regarding claim 2, Hoerold in view of You discloses the method of Claim 1, wherein removing the dummy metal lines comprises performing a subtractive metal etch of the dummy metal lines. Hoerold teaches removing dummy shapes / dummy metal lines in the BEOL flow. (See claim 2 (“removing dummy shapes”), ¶ [0059] (“removing metal wire”), and ¶¶ [0058]–[0060]). You teaches the use of dummy/extension patterns to regularize layout usage and occupy unused track space.
Regarding claim 7, Hoerold in view of You teach the method of Claim 1. Hoerold teaches a method of forming a BEOL region of an integrated circuit device including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines after performing the metal patterning, and forming vias thereafter. (See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
You teaches the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space in a cell-based semiconductor layout. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to form the top vias of Hoerold by performing subtractive top-via patterning after removing the dummy metal lines, because Hoerold already teaches the sequential removal of dummy metal lines followed by via formation in the BEOL flow, and one of ordinary skill would have understood the via patterning to be performed in a subtractive manner as a routine fabrication implementation of the already disclosed interconnect process of You. The claimed subtractive top-via patterning therefore merely describes an obvious and conventional way to form the top vias after dummy metal removal.
Accordingly, claim 7 would have been obvious over Hoerold in view of You.
Regarding claim 8, Hoerold in view of You teaches the method of Claim 7. Hoerold teaches a BEOL interconnect process including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines after performing the metal patterning, and forming vias thereafter. (See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
You teaches the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space in a cell-based semiconductor layout. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to implement the subtractive top-via patterning of claim 7 by selectively recessing top portions of certain non-dummy metal lines while blocking other non-dummy metal lines from the recessing, because such selective etch-and-mask processing is a predictable fabrication technique for forming different metal features in a BEOL interconnect stack after dummy metal removal. The claimed recessing and blocking operations therefore represent an obvious application of known patterning techniques to the interconnect flow taught by Hoerold, as informed by the regularized layout concepts of You.
Regarding claim 9, Hoerold in view of You disclose the method of Claim 8.
Hoerold teaches a BEOL interconnect process including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines after performing the metal patterning, and forming vias thereafter. (See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
You teaches the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space in a cell-based semiconductor layout. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to arrange the first top via and second top via to be laterally spaced apart and to provide a signal-line area opening between them, because such spacing and opening placement are routine layout choices used to accommodate selective subtractive top-via patterning and to maintain a regularized interconnect geometry after dummy metal removal. The claimed lateral spacing and intervening opening therefore amount to an obvious arrangement of known interconnect features.
Accordingly, claim 9 would have been obvious over Hoerold in view of You.
Regarding claims 10 and 11, Hoerold in view of You disclose the method of Claim 1.
Hoerold teaches a BEOL interconnect process including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines after performing the metal patterning, and forming vias thereafter. (See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
You teaches the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space in a cell-based semiconductor layout, thereby forming a more track-filled or full-track structure. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
With respect to claim 10, it would have been obvious to one of ordinary skill in the art at the time the invention was made that removing the dummy metal lines from the full-track standard cell would return the structure to the non-full-track standard cell configuration, because the full-track arrangement is created by the presence of the dummy/filler features and removal of those features necessarily restores the underlying layout.
With respect to claim 11, it would have further been obvious that, after removing the dummy metal lines, the signal lines of the non-full-track standard cell would have a constant pitch, because the remaining signal lines retain the regular spacing of the underlying standard-cell layout once the dummy lines are removed. Accordingly, claims 10 and 11 would have been obvious over Hoerold in view of You.
Regarding claim 12, Hoerold in view of You discloses the method of Claim 1.
Hoerold teaches a BEOL interconnect process including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines after performing the metal patterning, and forming vias thereafter. (See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
You teaches the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space in a cell-based semiconductor layout. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to first design the non-full-track standard cell before adding the dummy metal lines, because You teaches adding dummy and extension features during layout definition to fill openings in signal-line areas and regularize the cell geometry. Additionally to design the non-full-track standard cell and the dummy metal lines digitally, and to physically form the full-track standard cell during metal patterning based on the resulting design data is obvious, because such digital layout generation and subsequent physical fabrication are routine and conventional in semiconductor design and manufacturing.
Regarding claim 16, Hoerold discloses a method of forming a back-end-of-line (BEOL) region of an integrated circuit device, the method comprising (discloses a BEOL interconnect process including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines, and forming vias thereafter. See Hoerold, claim 2 and ¶¶ [0058]-[0060]):
designing non-dummy metal lines in respective signal-line areas of the BEOL region (Hoerold teaches metal lines and dummy metal shapes in an interconnect region See Hoerold, claim 2 and ¶¶ [0058]-[0060]);
performing metal patterning on the signal-line areas, after designing the dummy metal lines (teaches performing metal patterning after the dummy metal structures are added. See Hoerold, claim 2 and ¶¶ [0058]-[0060]);
removing the dummy metal lines after performing the metal patterning (teaches removing dummy metal lines after performing metal patterning. See Hoerold, claim 2 and ¶¶ [0058]-[0060]); and
forming a top via in at least one of the signal-line areas after removing the dummy metal lines (teaches forming vias thereafter following removal of the dummy metal lines. See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
Hoerold does not explicitly teach designing dummy metal lines in openings in at least some of the signal-line areas, after designing the non-dummy metal lines.
You teaches placing dummy and extension features in otherwise unused routing space / openings in a cell-based layout to regularize the layout. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the BEOL interconnect process of Hoerold in view of You to include designing non-dummy metal lines in signal-line areas, then designing dummy metal lines in openings of the signal-line areas, performing metal patterning, removing the dummy metal lines, and forming a top via thereafter, because Hoerold teaches the general BEOL dummy-line/metal-patterning/via-forming sequence and You teaches using dummy and extension features to regularize routing areas and occupy otherwise unused openings in a cell-based layout. Combining these teachings would have predictably resulted in the claimed BEOL region fabrication flow.
Regarding claim 18, Hoerold in view of You discloses the method of Claim 16.
Hoerold in view You further teaches wherein the signal-line areas are part of a standard cell of the BEOL region (You teaches cell-based semiconductor layouts and the use of dummy and extension features within routing regions of such layouts. See ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]. Hoerold teaches BEOL interconnect processing in a standard fabrication flow. See claim 2 and ¶¶ [0058]-[0060]).
and wherein, after removing the dummy metal lines, the standard cell is a non-full-track standard cell is taught by You (the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space, thereby providing a more track-filled or full-track standard-cell layout. See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[127]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to apply the Hoerold dummy-line/metal-patterning/via-forming BEOL process in the standard-cell routing environment taught by You, including arranging the signal-line areas as part of a standard cell and removing the dummy metal lines to achieve the desired track density. The combination would have predictably resulted in a non-full-track standard cell as a routine layout variation.
Regarding claim 19, Hoerold discloses a method of forming a back-end-of-line (BEOL) region of an integrated circuit device, the method comprising (Hoerold teaches a BEOL interconnect process including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines after performing the metal patterning, and forming vias thereafter. See claim 2 and ¶¶ [0058]-[0060]):
removing the dummy metal lines by performing a subtractive metal etch of the dummy metal lines (teaches removing dummy metal lines after performing metal patterning. See Hoerold, claim 2 and ¶¶ [0058]-[0060]); and
forming top vias after removing the dummy metal lines (Hoerold teaches forming vias thereafter following removal of the dummy metal lines. See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
Hoerold fails to teach providing a non-full-track standard cell design for the BEOL region; converting the non-full-track standard cell design to a full-track standard cell design by adding dummy metal lines to the non-full-track standard cell design, wherein adding the dummy metal lines comprises designing metal in all openings in signal-line areas of the non-full-track standard cell design.
You teaches providing a non-full-track standard cell design for the BEOL region (You teaches a cell-based semiconductor layout and the use of dummy and extension features in routing regions to regularize layout usage. See ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]);
converting the non-full-track standard cell design to a full-track standard cell design by adding dummy metal lines to the non-full-track standard cell design (You teaches adding dummy and extension features to occupy otherwise unused routing space in a cell-based layout, thereby increasing track usage. See ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]),
wherein adding the dummy metal lines comprises designing metal in all openings in signal-line areas of the non-full-track standard cell design (You teaches placing dummy and extension features in otherwise unused openings / routing space in the layout. See ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the BEOL interconnect process of Hoerold in view of You to provide a non-full-track standard cell design, add dummy metal lines in openings of signal-line areas to convert the design to a full-track standard cell design, remove the dummy metal lines by subtractive etch, and form top vias thereafter, because Hoerold teaches the dummy-line removal and via formation sequence and You teaches using dummy and extension features to regularize layout usage in a cell-based design.
Regarding claim 20, Hoerold in view of You teaches the method of Claim 19, further comprising:
before removing the dummy metal lines, performing metal patterning based on the full- track standard cell design (Hoerold teaches performing metal patterning before removing the dummy metal lines. See claim 2 and ¶¶ [0058]-[0060]. You teaches the use of dummy and extension features in a cell-based design to regularize layout usage. See ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127].,
wherein performing the metal patterning comprises forming the dummy metal lines (Hoerold teaches adding dummy metal shapes / dummy metal lines and performing metal patterning in connection therewith. See claim 2 and ¶¶ [0058]-[0060]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to perform metal patterning based on the full-track standard cell design before removing the dummy metal lines, wherein the metal patterning includes forming the dummy metal lines, as taught by Hoerold and You, because Hoerold teaches the relevant metal-patterning and dummy-line removal sequence and You teaches the underlying full-track style layout regularization. Accordingly, claim 20 would have been obvious over Hoerold in view of You.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Hoerold in view of You as applied to claim 2 above, and further in view of Huang et al. (US 2012/0288786 A1).
Hoerold in view of You teach method of Claim 2, as described above.
Furthermore, Hoerold in view of You teaches the removal of dummy metal features in a semiconductor interconnect process, thereby teaching the core limitation of removing the dummy metal lines. (See Hoerold, claim 2 and ¶ [0059]).
Huang teaches the use of dummy conductive fill patterns, breaker patterns, and etch-rule-driven layout constraints in a semiconductor design flow, including the use of pattern-dependent spacing and spacer-based masking concepts to control which regions are processed and which regions are protected during fabrication. (See Huang, e.g., ¶¶ [0025]-[0033], [0043]-[0058], [0071]-[0080]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the dummy-metal removal technique of Hoerold in view of You to employ a conventional blocking or masking pattern, as taught or suggested by the selective patterning and spacer-based fabrication techniques of Huang, in order to protect non-dummy metal lines where the subtractive etching of the dummy metal lines. The claimed blocking pattern, including its overlap relationship with non-dummy metal lines and its exclusion from dummy metal lines, is merely an obvious implementation of a known selective-etch protection strategy used to preserve desired metal features during removal of adjacent dummy features.
Accordingly, claim 3 would have been obvious over Hoerold in view of You and further view of Huang.
Regarding claim 4, Hoerold in view of You disclose the method of Hoerold teaches removing dummy metal features in a semiconductor interconnect process, including removing dummy shapes / dummy metal lines after performing metal patterning. (See Hoerold, claim 2 and ¶¶ [0058]-[0060]). You teaches the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space in a cell-based semiconductor layout. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
Huang teaches spacer-based and etch-rule-driven fabrication techniques in which protective and patterned structures are used to selectively control which regions are exposed and which regions are protected during processing. (See Huang, e.g., ¶¶ [0025]-[0033], [0043]-[0058], [0071]-[0080]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the dummy-metal removal process of Hoerold, as informed by You, to employ the selective protective/etch control techniques taught by Huang so that an insulating material is formed on the uppermost surfaces and sidewalls of the dummy and non-dummy metal lines, openings are etched in the insulating material to expose the uppermost surfaces of the dummy metal lines, and the dummy metal lines are then removed through the openings while the insulating material remains on the uppermost surfaces and sidewalls of the non-dummy metal lines. The claimed insulating material and opening formation merely constitute an obvious selective-etch implementation for protecting non-dummy metal features during removal of adjacent dummy metal lines.
Regarding claim 5, Hoerold in view of You and Huang disclose the method of Claim 4.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the selective dummy-metal removal process of Hoerold, as informed by You, to employ the protective/etch-control techniques taught by Huang so that the subtractive metal etch removes adjacent dummy metal lines while leaving the non-dummy metal lines protected by insulating material except at the exposed regions. In doing so, the etch would predictably sculpt the exposed end of the non-dummy metal line, and it is within the purview of one have ordinary skill that a resulting in a concave end portion is an obvious and expected outcome of the selective etch process. The claimed concave end portion is therefore merely an obvious result of performing the known subtractive etch under the controlled masking and exposure conditions taught by the cited references.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hoerold in view of You as applied to claim 2 above, and further in view of Xu et al. (US 10,354,912 B2).
Regarding claim 6, Hoerold in view You teaches the method of Claim 2, but does not explicitly teach what type of subtractive metal etch is used or what material it includes such as a subtractive ruthenium (Ru) etch as required by the claims.
Xu teaches that Ru is a known conductive BEOL material and that non-copper metals such as Ruthenium may be advantageous because they are easier to etch back. (See Xu, e.g., ¶¶ [23], [27], [37].
It would have been obvious to one of ordinary skill in the art at the time the invention was made to perform the subtractive metal etch of Hoerold in view of You on the dummy metal lines using a conductive BEOL material such as Ru, as suggested by the Xu via reference, because Ru was a known interconnect material and was identified as a material that is easier to etch back in BEOL fabrication. The recitation that the subtractive metal etch comprises a subtractive ruthenium (Ru) etch merely identifies a known conductive material for the dummy metal lines and a routine implementation choice for the known subtractive etch process.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hoerold in view of You as applied to claim 1 above, and further in view of KR 2022-0098901, hereafter KR ‘901.
Hoerold in view of You discloses the method of Claim 1.
Hoerold teaches a BEOL interconnect process including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines after performing the metal patterning, and forming vias thereafter. (See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
You teaches the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space in a cell-based semiconductor layout, thereby forming a more track-filled or full-track structure. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
KR ‘901 expressly discloses a semiconductor device fabrication method in which a metal pattern is formed by a self-aligned universal patterning (SAUP) process, including forming sacrificial patterns, spacers, trenches, and using selective spacer etching in the SAUP flow. (See KR 20220098901 A, Abstract; Description; Claims).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to perform the metal patterning of Hoerold’s full-track standard cell using SAUP, as taught by KR ‘901, because SAUP is a known and conventional patterning technique for forming metal patterns in semiconductor fabrication, and substituting one known metal-patterning technique for another would have been a predictable design choice yielding the same type of interconnect structure.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hoerold in view of You as applied to claim 1 above, and further in view of Chen et al. (US 10,825,726 B2).
Hoerold teaches a BEOL interconnect process including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines after performing the metal patterning, and forming vias thereafter. (See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
You teaches the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space in a cell-based semiconductor layout, thereby forming a more track-filled or full-track structure. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
Chen et al. expressly discloses that sidewall image transfer processes such as litho-etch-litho-etch (LELE) are typically used in BEOL processes for advanced design rules, and describes forming metal spacers, removing mandrels, and defining a final metal line pattern in an interconnect structure. (See ¶¶ [3], [19]-[21], [40]-[45], [59]-[63]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to perform the metal patterning of Hoerold’s full-track standard cell using LELE, as taught by Chen, because LELE is a known and conventional BEOL patterning technique suitable for defining metal line patterns in interconnect structures, and substituting one known patterning technique for another would have been a predictable design choice.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hoerold in view of You as applied to claim 1 above, and further in view of Mukesh et al. (US 2021/0280465 A1).
Hoerold teaches a BEOL interconnect process including adding dummy metal shapes / dummy metal lines, performing metal patterning, removing the dummy metal lines after performing the metal patterning, and forming vias thereafter. (See Hoerold, claim 2 and ¶¶ [0058]-[0060]).
You teaches the use of dummy and extension features to regularize layout usage and occupy otherwise unused routing space in a cell-based semiconductor layout, thereby forming a more track-filled or full-track structure. (See You, e.g., ¶¶ [0006]-[0008], [0037]-[0044], [0108]-[0118], [0124]-[0127]).
Mukesh discloses BEOL interconnect structures and methods in which the metal lines comprise, or may comprise, ruthenium (Ru), and further teaches self-aligned subtractive formation of top vias using line hardmasks and via hardmasks in a metal-line patterning flow. (See Abstract; ¶¶ [31], [43]-[45], [59]-[60].
It would have been obvious to one of ordinary skill in the art at the time the invention was made to perform the metal patterning of Hoerold’s full-track standard cell using Ru, as taught by Mukesh, because Ru was a known alternative BEOL interconnect metal and its use in the disclosed patterning flow would have been a predictable substitution for another known conductive material with no change in the basic patterning objective.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hoerold in view of You as applied to claim 16 above, and further in view of KR ‘901 and Mukesh.
Hoerold in view of You teaches the method of Claim 16,
Hoerold in view of You does not disclose wherein removing the dummy metal lines comprises performing a subtractive ruthenium (Ru) etch of the dummy metal lines, and wherein performing the metal patterning on the signal-line areas comprises performing self-aligned universal patterning (SAUP) on the signal-line areas.
Mukesh teaches BEOL interconnect structures in which the metal lines comprise ruthenium (Ru). (See ¶¶ [31], [43], [59]-[60]).
KR ‘901 expressly discloses a semiconductor device fabrication method in which metal patterning is performed using self-aligned universal patterning (SAUP). (See Abstract; Description).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to perform the metal patterning of Hoerold’s signal-line areas using SAUP, as taught by KR ‘901, because SAUP is a known semiconductor patterning technique for forming metal patterns.
It would have further been obvious to employ Ru in the metal-line/dummy-line fabrication flow, as Ru is disclosed by Mukesh as a known BEOL interconnect metal. Accordingly, claim 17 would have been obvious over Hoerold in view of You, further in view of KR ‘901 and Mukesh.
Conclusion
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/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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