Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 15202-000527-US
Filling Date: 05/01/24
Priority Date: 09/21/23
Inventor: Lee et al
Examiner: Bilkis Jahan
DETAILED ACTION
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-2, 4, 7-8, 10-12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US 2020/0006145 A1) in view of Lu et al (US 2024/0395903 A1).
Regarding claim 1, Li discloses a semiconductor device (Figures 2, 4, see annotated figure), comprising: a first semiconductor structure including a first substrate structure 102d, 102e and a first device layer (see annotated figure) on an upper surface of the first substrate structure 102d, 102e, the first device layer including a first region of the semiconductor device; and a second semiconductor structure 102a, 102b (Para. 34) including a second substrate structure and a second device layer on a lower surface of the second substrate structure 102a, 102b, the second device layer (see annotated figure) connected to the first device layer (connected through 102c) and including a second region of the semiconductor device, wherein the first substrate structure includes a first wafer 102e and a second wafer 102d on the first wafer 102e, the second wafer 102d is in contact with the first device layer (see annotated figure), the second substrate structure includes a third wafer 102b (Para. 34) and a fourth wafer 102a (Para. 34) on a lower surface of the third wafer 102b, the fourth wafer 102a is in contact with the second device layer (see annotated figure).
Li does not explicitly disclose an upper surface of the second wafer is a (100) crystal plane.
However, Lu discloses an upper surface of the second wafer is a (100) crystal plane (Para. 13). Lu teaches the above modification is used to obtain projection of the crystal orientation (Para. 39). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Li wafer with Lu wafer crystal plane as suggested above to obtain projection of the crystal orientation (Para. 39).
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Regarding claims 2 and 4, Lu discloses the semiconductor device of claim 1, wherein a lower surface of the fourth wafer is a (100) crystal plane; the semiconductor device of claim 1, wherein an upper surface of the first wafer is a (111) crystal plane (Para. 13).
Regarding claims 7 and 8, Lu discloses the semiconductor device of claim 1, wherein a lower surface of the third wafer is a (111) crystal plane; the semiconductor device of claim 1, wherein a lower surface of the third wafer is a (100) crystal plane (Para. 13).
Regarding claim 10, Li discloses the semiconductor device of claim 1, wherein the first region 104 (Fig. 4, Para. 39, see annotated figure, “1st device layer”) includes a transistor 302, and the second region (see annotated figure, “2ndt device layer”)) includes an interconnection structure 314 (Para. 41) electrically connected to the transistor.
Regarding claim 11, Li discloses the semiconductor device of claim 1, wherein the first device layer 104 further includes a first bonding metal layer 314 on the first region, and the second device layer 104 further includes a second bonding metal layer 314 below the second region, and the second bonding metal layer is bonded to the first bonding metal layer (bonded through 102c).
Regarding claim 12, Li does not explicitly disclose the semiconductor device of claim 1, wherein the second wafer has a thickness in a range of 1 μm to 5 μm.
However, Li discloses a particular thickness of the wafer 102d (Fig. 2). Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the second wafer has a thickness in a range of 1 μm to 5 μm for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the thickness.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 18, Li discloses a semiconductor device (Figs. 2, 4, see annotated figure), comprising: a first semiconductor structure including a first substrate structure 102e, 102d, a first region 104 (see annotated figure, “1st device layer”) of the semiconductor device on an upper surface of the first substrate structure, and a first bonding metal layer 314 on the first region 104; and a second semiconductor structure including a second substrate structure, a second region (see annotated figure, “2nd device layer”) of the semiconductor device on a lower surface of the second substrate structure, and a second bonding metal layer below the second region and bonded to the first bonding metal layer (bonded through 102c, claim does not specify directly bonding), wherein the first substrate structure and the second substrate structure each include a plurality of wafers stacked vertically (Fig. 2).
Allowable Subject Matter
4. Claims 3, 5-6, 9, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
5. Claims 13-16 and 17 are allowed.
6. The following is an examiner’s statement of reasons for allowance:
7. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed semiconductor device, comprising: the first substrate structure includes a plurality of wafers stacked vertically, and in the first substrate structure, the plurality of wafers are stacked such that upper surfaces thereof have a same crystal plane and crystal directions are tilted with respect to each other or a portion of upper surfaces of the plurality of wafers have different crystal planes in combination with all other limitations as recited in claim 13.
8. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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