DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-14 in the reply filed on 7/28/26 is acknowledged. The traversal is on the ground(s) that the search and examination of the entire claims can be made without serious burden. The argument does not directly address the reason for the restriction as previously indicated, in two separate classification areas (see the previous office action.) Thus, this is not found persuasive.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (US 2008/0079115.)
In regard to claims 1 and 8, in figs. 5-13, Wang discloses an apparatus (semiconductor device), comprising:
a memory package comprising a substrate 200 and a plurality of memory layers (layers above the substrate, fig. 11);
a plurality of conductive nodes 964, for example, connected by a plurality of conductive traces 96 to form a first portion of an induction device, wherein the first portion of the inductive device comprises an inductive coil within at least two layers of the plurality of memory layers of the memory package, fig. 8; and
a plurality of bond traces to couple a first portion of the plurality of conductive nodes to a second portion of the plurality of conductive nodes to form a second portion of the inductive device, fig. 8, wherein the second portion of the inductive device comprises an inductive bond wire at 1122/1124 in a physical area that is physically outside the memory package, fig. 12.
Furthermore, the device as disclosed by Wang is capable of receiving signaling having a first voltage value associated therewith, and apply signaling having a second voltage value associated therewith to the controller.
Regarding claims 2 and 11, wherein the plurality of bond traces each include a plurality of parallel bond traces. Fig. 8.
Regarding claims 3 and 13, wherein the plurality of bond traces formed an arc above an aperture of the memory package. See figs. 8 and 9.
Regarding claim 4, wherein the memory package includes a first portion along a first edge of the plurality of conductive nodes and a second portion along a second edge of the plurality of conductive nodes. Fig. 8.
Regarding claim 5, wherein the first portion of the memory package separates a portion of the plurality of conductive traces from the plurality of bond traces. Figs. 5 and 8.
Regarding claim 6, wherein the inductive coil is capable of generating a first quantity of induction and the inductive bond wire generates a second quantity of induction.
Regarding claim 7, wherein the first quantity of induction and the second quantity of induction are capable of being utilized to form a DC/DC boost converter circuit.
8. (Original) A system, comprising: a controller resident on a memory device; and an induction apparatus resident on the memory device, the induction apparatus comprising:
a first plurality of conductive nodes connected to a second plurality of conductive nodes by a plurality of conductive traces to form an inductive;
a plurality of bond traces to couple the first plurality of conductive nodes to the second plurality of conductive nodes to form an inductive bond wire; and
a memory package positioned between the plurality of conductive traces and the plurality of bond traces, wherein the induction apparatus is configured to:
receive signaling having a first voltage value associated therewith, and apply signaling having a second voltage value associated therewith to the controller.
Regarding claims 9 and 10, Wang further discloses the plurality of conductive traces are capable of generating a first inductance from the received signaling having the first voltage and the plurality of bond traces generate a second inductance from the received signaling having the first voltage.
Regarding claim 12, wherein the memory package includes an aperture between a portion of the plurality of conductive traces and the plurality of bond traces. Figs. 5 and 8.
Regarding claim 14, wherein a non-conductive material 244, for example, is positioned between the memory package and the plurality of bond traces. Figs. 8 and 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN W HA/Primary Examiner, Art Unit 2814
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