DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, and 3 thru 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. US 2024/0021488 A1 in view of Lee et al. US 2019/0385982 A1. Sun discloses (see, for example, Figure 9) an interposer comprising: a core layer 102; an upper wiring layer 112/114/113A/113B/113C on the core layer 102; a lower pad 105 on a bottom surface of the core layer 102; a through via 110 that vertically penetrates the core layer and connects the upper wiring layer 112/113A/113B/113C to the lower pad 105; and a dummy structure on a lower portion of the core layer 102, wherein the dummy structure comprises: dummy layer 111; a barrier layer (see, for example, paragraph [0021] wherein Sun discloses including a barrier layer) between the core layer 102 and the dummy layer 111; and wherein the dummy structure is horizontally spaced apart from the through via 110 and is electrically insulated from the through via 110. In paragraph [0019], Sun discloses the dummy layer 111. Sun does not disclose a dielectric layer between the core layer and the barrier layer. However, Lee discloses (see, for example, FIG. 8, and paragraph [0082]) a TSV, which includes a dummy TSV 114 that further includes a dielectric liner and diffusion barrier 604 inside a silicon core 104. In paragraph [0064], Lee discloses the dielectric liner (i.e. dielectric layer) and diffusion barrier 604 prevents diffusion of the metal of the TSV 114. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a dielectric layer between the core layer and the barrier layer in order to prevent metal diffusion of the dummy layer.
Sun does not clearly disclose: a dummy layer comprising a bottom surface that is coplanar with the bottom surface of the core layer. However, in Figure 9, Sun discloses a dummy layer 111 that is within a core layer 102, and to extend the depth of the dummy layer 111 to the bottom surface of the core layer 102 would have been an obvious design modification to improve the heat dissipation of the dummy layer by increasing its surface area. Therefore, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a dummy layer comprising a bottom surface that is coplanar with the bottom surface of the core layer in order to improve the heat dissipation by increasing the surface area as a matter of obvious design choice according to the preferences of the user. Further, a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 3, see, for example, Figure 9 wherein Sun discloses a first passivation layer containing the device 103.
Regarding claim 4, Sun in view of Lee does not disclose a bottom surface of the first passivation layer being coplanar with a bottom surface of the through via; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a bottom surface of the first passivation layer being coplanar with a bottom surface of the through via in order to ease the manufacturing steps by contacting the through via directly to a lower pad at a top of a dielectric layer, and further to decrease the length of the through via according to the preferences of the user. Further, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 5, see, for example, Figure 9 wherein Sun discloses a second passivation layer 104, and exposes a portion of the bottom surface of the lower pad 105.
Regarding claim 6, Sun in view of Lee does not clearly disclose each of the first passivation layer and the second passivation layer comprises silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON); however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have each of the first passivation layer and the second passivation layer comprises silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON) in order to adequately insulate the metallization patterns, and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 7, see, for example, Figure 9 wherein Sun discloses the dummy structure (i.e. the middle dummy layer) 111 being vertically spaced apart from the upper wiring layer 114 and is electrically insulated from the upper wiring layer 114.
Regarding claims 8, and 16, Sun in view of Lee does not disclose a height of the dummy layer being in a range of about 1 μm to about 10 μm; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a height of the dummy layer being in a range of about 1 μm to about 10 μm in order to adequately dissipate heat, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 9, see, for example, Figure 9 wherein Sun discloses the dummy layer 111 having a linear shape, etc.
Regarding claim 10, Sun in view of Lee does not disclose the dummy layer comprises tungsten (W), copper (Cu), or aluminum (Al); however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the dummy layer comprises tungsten (W), copper (Cu), or aluminum (Al) in order to have a conductive material well known for dissipating heat, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 11, Sun in view of Lee does not disclose the barrier layer comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN); however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the barrier layer comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) in order to have a material that shields the metal in the dummy layer from diffusing, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 12, see , for example, Figure 9 wherein Sun discloses a semiconductor package comprising: a package substrate 181; an interposer 102 on the package substrate 181; a semiconductor chip 160 on the interposer 102; and a chip stack 150 on the interposer 102 and horizontally spaced apart from the semiconductor chip 160, wherein the interposer comprises: a core layer 102; an upper wiring layer 104 on the core layer 102; a dummy structure 111 in the core layer 102; a passivation layer (i.e. the layer that contains the device 103) that covers the dummy structure 111 and the bottom surface of the core layer 102; a through via 110 that vertically penetrates the core layer 102 and the passivation layer 103 and is connected to the upper wiring layer 104; and a lower pad 105 on the bottom surface of the core layer 102, wherein the lower pad 105 is connected to the through via 110, wherein the dummy structure 111 is vertically spaced apart from the upper wiring layer 104, and wherein the dummy structure 111 is electrically insulated from the upper wiring layer 104. Sun in view of Lee does not clearly disclose a dummy structure … exposed on a bottom surface of the core layer; however, extending the depth of the dummy layer 111 to the bottom surface of the core layer 102 would have been an obvious design modification to improve the heat dissipation of the dummy layer by increasing its surface area. Therefore, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a dummy structure … exposed on a bottom surface of the core layer in order to improve the heat dissipation by increasing the surface area as a matter of obvious design choice according to the preferences of the user. Further, a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 13, see, for example, Figure 9 wherein Sun discloses the dummy structure 111 being horizontally spaced apart from the through via 110, and being electrically insulated from the through via 110.
Regarding claims 14, and 15, see, for example, the rejection of claim 1 above wherein Sun discloses (see, for example, paragraph [0021]) a barrier layer, and Lee discloses (see, for example, FIG. 8, and paragraph [0082]) a dielectric layer.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The references of record, either singularly or in combination, do not teach or suggest at least an interposer comprising: the barrier layer covers a top surface of the dummy layer and a lateral surface of the dummy layer, wherein the dielectric layer covers a top surface of the barrier layer and a lateral surface of the barrier layer, and wherein a lowermost end of the barrier layer, a lowermost end of the dielectric layer, and the bottom surface of the core layer are at a same vertical level.
Claims 17 thru 20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least an interposer comprising: a core layer; an upper wiring layer on a top surface of the core layer, the upper wiring layer comprising a dummy structure on a lower portion of the core layer; a first passivation layer that covers the dummy structure and a bottom surface of the core layer; a bottom surface of the through via is coplanar with a bottom surface of the first passivation layer; a lower pad on the bottom surface of the first passivation layer and connected to the through via; a second passivation layer that covers the bottom surface of the first passivation layer and comprises a recess exposing a portion of a bottom surface of the lower pad; and an under-bump pattern on the recess, wherein the dummy structure comprises: a dummy layer comprising a bottom surface that is coplanar with the bottom surface of the core layer; a conductive layer that covers a top surface of the dummy layer and a lateral surface of the dummy layer, wherein a lowermost surface of the conductive layer is coplanar with the bottom surface of the core layer; and a dielectric layer that covers a top surface of the conductive layer and a lateral surface of the conductive layer, wherein a lowermost surface of the dielectric layer is coplanar with the bottom surface of the core layer.
- The closest references, Sun et al. US 2024/0021488 A1, and Lee et al. US 2019/0385982 A1 discloses an interposer, and semiconductor package, but fails to disclose the above-cited limitations as cited above.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
June 5, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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