DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirao et al. (Hirao, US 5,657,2023).
Regarding claim 1, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising: a semiconductor element ( see device connector 84/82 in FIG. 1); and a first terminal (terminal 63 in FIG. 1 with respect to FIG. 12) electrically connected to the semiconductor element ( by connector element 84/82), wherein the first terminal (terminal 63 in FIG. 1) includes a first portion ( terminal portion 63c in FIG. 12) at least a portion of which extends in a first direction and a second portion extending in the first direction (see FIG. 2 i.e. element 63c comprises x and y direction), and the second portion ( opposite of terminal portion 63c) overlaps with the first portion as viewed in a second direction orthogonal to the first direction (see terminal 63c in FIG. 12).
Regarding claim 2, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the first terminal includes a third portion (terminal portion 63b) connecting the first portion and the second portion ( terminal portion 63c).
Regarding claim 3, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the third portion ( terminal portion 63b) protrudes beyond the first portion and the second portion as viewed in the first direction (see FIG. 12).
Regarding claim 4, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the second portion (terminal portion 63c) is spaced apart from the first portion ( both side of terminal 63c comprises space as shown in FIG. 12).
Regarding claim 5, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the first terminal includes a fourth portion (terminal portion 63a/63d) located on a side opposite to the third portion in the first direction with respect to the second portion and connected to the second portion, and the fourth portion extends in the second direction toward a side opposite to the first portion (see FIG. 1 with respect to FIG. 12).
Regarding claim 6, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) further comprising a sealing resin (silicon gel 16) covering a portion of the first terminal (terminal 63) and the semiconductor element, wherein the first portion extends from the sealing resin, and the second portion is spaced apart from the sealing resin (see FIG. 1 with respect to FIG. 12).
Regarding claim 7, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the sealing resin ( silicon gal 16) overlaps with the first portion and the second portion (terminal portion 63c ) as viewed in the first direction (see FIG. 1 with respect to FIG. 12).
Regarding claim 8, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, further comprising a second terminal (terminal 61 in FIG. 1) extending in the first direction and including a portion covered with the sealing resin (silicon gal 16), wherein the second terminal (terminal 61) is spaced apart from the first terminal (terminal 63) in a third direction orthogonal to the first direction and the second direction (see FIG. 1), the second terminal includes a first mounting portion extending from the sealing resin and a second mounting portion located on a side opposite to the sealing resin in the first direction with respect to the first mounting portion and connected to the first mounting portion, and a dimension of the second mounting portion in the third direction is smaller than a dimension of the first mounting portion in the third direction (see FIG. 1 with respect to FIG. 12).
Regarding claim 9, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the first mounting portion overlaps with the first portion as viewed in the third direction (see FIG. 1 with respect to FIG. 12).
Regarding claim 10, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the first mounting portion includes a first edge extending in the third direction to be connected to the second mounting portion, and the second portion lies on both sides of the first edge in the first direction(see FIG. 1 with respect to FIG. 12).
Regarding claim 11, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) further comprising a die pad ( pad 84), wherein the semiconductor element is electrically bonded to the die pad (pad 84).
Regarding claim 12, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the first terminal (terminal 63) is connected to the die pad (pad 84).
Regarding claim 13, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the die pad (pad 84) includes a reverse surface facing opposite to the semiconductor element in the second direction, and the reverse surface is exposed from the sealing resin ( silicon gal 16).
Regarding claim 14, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein; a wiring board (I circuit board 52) including a substrate and a wiring (wiring 54) disposed on the substrate; and a bonding layer electrically bonding the wiring and the first terminal, wherein the substrate includes a through-hole adjacent to the wiring and extending in the first direction through the substrate, and a portion of the first portion and a portion of the second portion are accommodated in the through-hole (see FIG. 1).
Regarding claim 15, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the through-hole is a slotted hole extending in the second direction (see FIG. 1).
Regarding claim 16, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) comprising, wherein the first portion is located between the sealing resin and the second portion in the second direction (see FIG. 1).
Regarding claim 17, Hirao shows a semiconductor device ( device assembly 1 in FIG. 1) further comprising a heat dissipating member (element 10 in FIG. 1), wherein the heat dissipating member is attached to the sealing resin (silicon gal 16).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893
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