Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20140356635), in view of Sugiyama (US 20180310401).
Regarding claim 1, Kim discloses an electronic device (200, Fig. 2; 300, Fig. 3) comprising:
a printed circuit board (the circuit board with layers and components, Fig. 3) including a plurality of layers (layers 306, 310, 312, 314, 304),
wherein the plurality of layers includes at least one metal layer (trace layer 314), and at least one core layer (the core layer 304),
wherein the at least one core layer includes core material (the first and second core 304a, 304b) and a coefficient of thermal expansion (CTE) adjustment structure (the first and second inorganic core layers 308, 309) extending along a first lateral direction and between the core material, and
wherein the CTE adjustment structure includes a material different from the core material (the core 304a and 304b may be made from glass, resin, fiberglass, and/or epoxy) and configured to reduce an overall CTE of the printed circuit board (the material of the core 308 and 309 may be ceramic, glass or silicon; paragraph 76);
one or more components (components 302) mounted on the printed circuit board.\
Kim does not explicitly disclose the CTE adjustment structure directly contacting at least one peripheral surface of the core material.
Sugiyama suggests all the elements inside the core substrate (11, Fig. 2) are directly contacting each other by the peripheral surfaces.
It would have been obvious to one having skill in the art at the effective filing date of the invention to arrange the components in the circuit board in order to fit all the components in the limited space of the circuit substrate.
Regarding claim 2, Kim discloses the claimed invention as set forth in claim 1. Kim further suggests the CTE adjustment structure has a CTE value below 5 ppm/° C. (the properties of ceramic or silicon material made of the core 308 & 309 are around this value; i.e., Silicon nitride 3.7 ppm/° C; silicon 2.6 ppm/° C), and wherein the plurality of layers includes at least one prepreg layer (paragraph 5).
Regarding claim 3, Kim discloses the claimed invention as set forth in claim 1. Kim further suggests the CTE adjustment structure includes a first linear portion (308) extending along the first lateral direction and a second linear portion (309) extending along a second lateral direction of the printed circuit board, wherein a first dimension of the printed circuit board in the first lateral direction is greater than a second dimension of the printed circuit board in the second lateral direction (assuming the cut off line is from at the border of 309 dividing the left side and the right side of the circuit board, then the left side has greater dimension than the right side).
Regarding claim 4, Kim discloses the claimed invention as set forth in claim 1. Kim suggests the CTE adjustment structure is a first CTE adjustment structure (308); and the printed circuit board includes in the at least one core layer a second CTE adjustment structure (309) separate from the first CTE adjustment structure, wherein a combination of the first and second CTE adjustment structures are for having the overall CTE below a CTE threshold value (the CTE of 308 and 309 is less than 5 ppm/° C).
Regarding claim 5, Kim discloses the claimed invention as set forth in claim 1. Kim further suggests the first lateral direction is a longitudinal direction of the printed circuit board (Fig. 3).
Regarding claim 6, Kim discloses the claimed invention as set forth in claim 1.
Kim does not explicitly disclose a length of the CTE adjustment structure is at least half of a total length of the printed circuit board.
Kim suggests the size of the structure (208, 308, 309) may be adjusted (Figs. 2 – 68E).
It would have been obvious to one having skill in the art at the effective filing date of the invention to adjust the size of a components on the substrate in order to form a functional circuit board.
Regarding claim 7, Kim discloses the claimed invention as set forth in claim 1. Kim further suggests the CTE adjustment structure includes silicon or ceramic (paragraph 76).
Regarding claim 8, Kim discloses the claimed invention as set forth in claim 1. Kim further suggests the CTE adjustment structure is located below the one or more components (308 and 309 are below the component 302, Fig. 3) or adjacent to a footprint of the one or more components for reducing a mismatch or a difference in the overall CTE for the printed circuit board and the one or more components.
Regarding claim 9, Kim discloses the claimed invention as set forth in claim 8. Kim further suggests the CTE adjustment structure has a CTE value (silicon nitride 3.0 ppm/° C) that is between a CTE value of the one or more components (silicon 2.6 ppm/° C) and a CTE value of the core material (glass 5.5 ppm/° C) and/or closer to the CTE value of the one or more components than the CTE value of the core material.
Regarding claim 10, Kim discloses the claimed invention as set forth in claim 8. Kim further suggests the one or more components include a memory, a processor, or both (integrated circuit die; paragraph 5); at least a portion of the CTE adjustment structure located below or adjacent to the footprint of the memory, the processor, or both.
Regarding claim 11, Kim discloses a printed circuit board comprising:
at least one metal layer (trace layer 314, 316; Fig. 3); and
at least one core layer (the core layer 304) attached to the at least one metal layer and including (1) core material (the core 304a and 304b may be made from glass, resin, fiberglass, and/or epoxy) and (2) at least one coefficient of thermal expansion (308, 309, Fig. 3) adjustment structure extending along a first lateral direction and between the core material, wherein the CTE adjustment structure includes a material different from the core material (the material of the core 308 and 309 may be ceramic, glass or silicon; paragraph 76) and configured to reduce an overall CTE of the printed circuit board, and wherein a length, a width, a location, or a combination thereof of the CTE adjustment structure is based on one or more planned locations for mounting components on the printed circuit board (the structure 308 is planned to be below the component 302).
Kim does not explicitly disclose the CTE adjustment structure directly contacting at least one peripheral surface of the core material.
Sugiyama suggests all the elements inside the core substrate (11, Fig. 2) are directly contacting each other by the peripheral surfaces.
It would have been obvious to one having skill in the art at the effective filing date of the invention to arrange the components in the circuit board in order to fit all the components in the limited space of the circuit substrate.
Regarding claim 12, Kim discloses the claimed invention as set forth in claim 11. Kim further suggests at least a portion of the CTE adjustment structure is overlapped by or is within a predetermined distance from the one or more planned mounting locations (the structure 308 is overlapped component 302), and wherein the printed circuit board includes at least one prepreg layer (paragraph 5) attached to the at least one metal layer.
Regarding claim 13, Kim discloses the claimed invention as set forth in claim 11. Kim further suggests the at least one core layer includes: a first layer (layer 306) having the core material and the at least one CTE adjustment structure (308, 309) arranged coplanar with each other, wherein the core material comprises a first core material (the core 304a and 304b may be made from glass, resin, fiberglass, and/or epoxy) and the at least one CTE adjustment structure comprises a first CTE adjustment structure (308); and a second layer (bottom side of 306) having a second core material (material of 306) and a second CTE adjustment structure (309) arranged coplanar to each other and over the first layer, wherein the second CTE adjustment structure overlaps the first core material (looking from the side, 309 is overlapping 304a and 308), the first CTE adjustment structure, or both for providing a targeted CTE level at one or more overlapping portions.
Regarding claim 14, Kim discloses the claimed invention as set forth in claim 11. Kim further suggests the CTE adjustment structure includes silicon or ceramic (the material of the core 308 and 309 may be ceramic, glass or silicon; paragraph 76) for offsetting a CTE of the core material (glass) and produce the overall CTE to be closer to a CTE of silicon-based components (silicon material of 308 is closer to silicon-based component than glass).
Regarding claim 15, Kim discloses a method for controlling a coefficient of thermal expansion (CTE) of a printed circuit board, the method comprising:
determining a set of dimensions for the printed circuit board (set dimension for the circuit board 300, Fig. 3); and
determining an arrangement of core material (core 304) and one or more CTE adjustment structures (308, 309) in a core layer,
wherein the one or more CTE adjustment structures is adjacent to and coplanar with the core material (Fig. 3),
wherein the CTE adjustment structure includes material different from the core material (the core 304a and 304b may be made from glass, resin, fiberglass, and/or epoxy) and configured to reduce the CTE of the printed circuit board (low CTE of glass, resin, fiberglass and epoxy), and
wherein determining the arrangement includes deriving a shape, a set of dimensions, and a position for each of the one or more CTE adjustment structures (determine the size and shape of 308) according to a targeted CTE for the printed circuit board or portions thereof (position the components as shown in Fig. 3).
Kim does not explicitly disclose the CTE adjustment structure directly contacting the core material.
Sugiyama suggests all the elements inside the core substrate (11, Fig. 2) are directly contacting each other by the peripheral surfaces.
It would have been obvious to one having skill in the art at the effective filing date of the invention to arrange the components in the circuit board in order to fit all the components in the limited space of the circuit substrate.
Regarding claim 16, Kim discloses the claimed invention as set forth in claim 15. Kim further suggests determining component (302) locations on the printed circuit board, the component locations configured to receive one or more components (302), wherein the shape, the set of dimensions, and the position for each of the one or more CTE adjustment structures is derived based on the component locations (determine the size, shape and location of components 302).
Regarding claim 17, Kim discloses the claimed invention as set forth in claim 16. Kim further suggests wherein the shape, the set of dimensions, and the position for each of the one or more CTE adjustment structures (determine size, shape and location of 308) are derived based on iteratively: adjusting at least one of the shape, the set of dimensions, and the position; calculating an estimated CTE or a corresponding warpage measure for the printed circuit board or a portion thereof; and evaluating the estimated CTE based on a predetermined acceptance threshold (evaluate the position of 308).
Regarding claim 18, Kim discloses the claimed invention as set forth in claim 16. Kim further suggests determining the arrangement includes: identifying a location for a via (determine the location for the vias 326) associated with the determined component locations; and locating the one or more CTE adjustment structures to avoid overlapping with the via location (Fig. 3).
Regarding claim 19, Kim discloses the claimed invention as set forth in claim 15. Kim further suggests manufacturing the printed circuit board based on: arranging the core material (the core 304a and 304b may be made from glass, resin, fiberglass, and/or epoxy) and the one or more CTE adjustment structures (308, 309) according to the determined arrangement; attaching a metal layer (314, 316) to the core material and the one or more CTE adjustment structures; and forming a prepreg layer (paragraph 5) over the metal layer.
Regarding claim 20, Kim discloses the claimed invention as set forth in claim 15. Kim further suggests the shape, the set of dimensions, and the position for each of the one or more CTE adjustment structures is identified using a computing model configured to estimate a warpage measure associated with component locations and the arrangement based on at least one dataset representative of previous warpage results associated with previously determined shapes, dimensions, and positions CTE adjustment structures (determine the size, shape and location of 308 to avoid warpage of the components by having material around 308 to keep 308 in place).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wu (US 20200137871) discloses a circuit board, core layer and a structure inside the core layer, Fig. 1G.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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