DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mori(USPGPUB DOCUMENT: 2019/0371885, hereinafter Mori) in view of Aketa (USPGPUB DOCUMENT: 2020/0144209, hereinafter Aketa).
Re claim 1 Mori discloses a semiconductor device comprising: a chip(2) that has a main surface; a main surface electrode(37/75/56/57) that is arranged on the main surface; and a sealing insulator(21) that covers the electrode, and that has a portion directly covering the main surface electrode(37/75/56/57) (since 21 overlays or overlies, this may be interpreted as covering).
Mori does not disclose a semiconductor device comprising: a terminal electrode that is arranged on the main surface electrode(37/75/56/57) such as to expose a part of the main surface electrode(37/75/56/57); and a sealing insulator that covers a periphery of the terminal electrode such as to expose a part of the terminal electrode, and that has a portion directly covering the main surface electrode(37/75/56/57).
Aketa disclose a semiconductor device comprising: a terminal electrode(43/45/47 of Aketa); and a sealing insulator(8 of Aketa) that covers a periphery of the terminal electrode such as to expose a part of the terminal electrode.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Aketa to the teachings of Mori in order to have an electronic component and a semiconductor device with which downsizing and an improvement in heat dissipation [0007, Aketa]. In doing so, a terminal electrode(43/45/47 of Aketa) that is arranged on the main surface electrode(37/75/56/57) such as to expose a part of the main surface electrode(37/75/56/57); and a sealing insulator(8 of Aketa) that covers a periphery of the terminal electrode such as to expose a part of the terminal electrode, and that has a portion directly covering (since 8 of Aketa overlays or overlies, this may be interpreted as covering) the main surface electrode(37/75/56/57).
Re claim 2 Mori and Aketa disclose the semiconductor device according to Claim 1, wherein the sealing insulator(8 of Aketa) includes resin[0068 of Aketa] and a plurality of fillers.
Re claim 3 Mori and Aketa disclose the semiconductor device according to Claim 2, wherein the resin[0068 of Aketa] consists of a thermosetting resin[0068 of Aketa].
Re claim 4 Mori and Aketa disclose the semiconductor device according to Claim 1, wherein the terminal electrode(43/45/47 of Aketa) is thicker than the chip(2), and the sealing insulator(8 of Aketa) is thicker than the chip(2).
Re claim 5 Mori and Aketa disclose the semiconductor device according to Claim 1, wherein the terminal electrode(43/45/47 of Aketa) exposes a corner portion of the main surface electrode(37/75/56/57), and the sealing insulator(8 of Aketa) directly covers the corner portion of the main surface electrode(37/75/56/57).
Re claim 6 Mori and Aketa disclose the semiconductor device according to Claim 1, wherein the main surface electrode(37/75/56/57) has an electrode surface and an electrode side wall, the terminal electrode(43/45/47 of Aketa) exposes the electrode surface and the electrode side wall, and the sealing insulator(8 of Aketa) directly covers the electrode surface and the electrode side wall.
Re claim 7 Mori and Aketa disclose the semiconductor device according to Claim 1, wherein the sealing insulator(8 of Aketa) has a portion in contact only with the main surface electrode(37/75/56/57) and the terminal electrode(43/45/47 of Aketa) on the main surface electrode(37/75/56/57).
Re claim 8 Mori and Aketa disclose the semiconductor device according to Claim 1, wherein the terminal electrode(43/45/47 of Aketa) has a terminal surface, and the sealing insulator(8 of Aketa) has an insulating main surface that forms a single flat surface with the terminal surface.
Re claim 9 Mori and Aketa disclose the semiconductor device according to Claim 1, wherein the chip(2) has a side surface, and the sealing insulator(8 of Aketa) has an insulating side wall that forms a single flat surface with the side surface.
Re claim 10 Mori and Aketa disclose the semiconductor device according to Claim 1, wherein the chip(2) includes a monocrystal of a wide bandgap semiconductor.
Re claim 11 Mori discloses a semiconductor device comprising: a chip(2) that has a main surface; a main surface electrode(37/75/56/57) that is arranged on the main surface; an insulating film(21) that has a single layered structure comprising an inorganic film or an organic film(Although Mori is silent as to what material the insulating film(21) may be, since the only two options are for a material to be either an organic material or alternatively a "non-organic" material, Mori satisfies the limitation), and that directly covers the main surface electrode(37/75/56/57) (since 21 overlays or overlies, this may be interpreted as covering) such as to expose a part of the main surface electrode(37/75/56/57);
Mori does not disclose a terminal electrode that is arranged on the main surface electrode(37/75/56/57); and a sealing insulator that covers a periphery of the terminal electrode such as to expose a part of the terminal electrode, and that has a portion directly covering the insulating film.
Aketa disclose a terminal electrode(43/45/47 of Aketa); and a sealing insulator(8 of Aketa) that covers a periphery of the terminal electrode.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Aketa to the teachings of Mori in order to have an electronic component and a semiconductor device with which downsizing and an improvement in heat dissipation [0007, Aketa]. In doing so, a terminal electrode(43/45/47 of Aketa) that is arranged on the main surface electrode(37/75/56/57); and a sealing insulator(8 of Aketa) that covers a periphery of the terminal electrode such as to expose a part of the terminal electrode, and that has a portion directly covering the insulating film.
Re claim 12 Mori and Aketa disclose the semiconductor device according to Claim 11, wherein the sealing insulator(8 of Aketa) includes resin[0068 of Aketa] and a plurality of fillers.
Re claim 13 Mori and Aketa disclose the semiconductor device according to Claim 11, wherein the insulating film has a single layered structure comprising an oxide film, a nitride film, an oxynitride film, or a photosensitive resin[0068 of Aketa] film.
Re claim 14 Mori and Aketa disclose the semiconductor device according to Claim 11, wherein the terminal electrode(43/45/47 of Aketa) is thicker than the chip(2), and the sealing insulator(8 of Aketa) is thicker than the chip(2).
Re claim 15 Mori and Aketa disclose the semiconductor device according to Claim 11, wherein the insulating film directly covers at least a part of a corner portion of the main surface electrode(37/75/56/57), and the sealing insulator(8 of Aketa) covers at least a part of the corner portion of the main surface electrode(37/75/56/57) across the insulating film.
Re claim 16 Mori and Aketa disclose the semiconductor device according to Claim 11, wherein the main surface electrode(37/75/56/57) has an electrode surface and an electrode side wall, the insulating film directly covers the electrode surface and the electrode side wall, and the sealing insulator(8 of Aketa) covers the electrode surface and the electrode side wall across the insulating film.
Re claim 17 Mori and Aketa disclose the semiconductor device according to Claim 11, wherein the terminal electrode(43/45/47 of Aketa) has a portion that is positioned on the main surface electrode(37/75/56/57) and a portion that is positioned on the insulating film.
Re claim 18 Mori and Aketa disclose the semiconductor device according to Claim 11, wherein the terminal electrode(43/45/47 of Aketa) has a terminal surface, and the sealing insulator(8 of Aketa) has an insulating main surface that forms a single flat surface with the terminal surface.
Re claim 19 Mori and Aketa disclose the semiconductor device according to Claim 11, wherein the chip(2) has a side surface, and the sealing insulator(8 of Aketa) has an insulating side wall that forms a single flat surface with the side surface.
Re claim 20 Mori and Aketa disclose the semiconductor device according to Claim 11, wherein the chip(2) includes a monocrystal of a wide bandgap semiconductor.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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