Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by YANAGIDA (2020027383).
Regarding claim 1, YANAGIDA teaches a manufacturing method for a semiconductor device comprising:
a step of preparing a wafer source (fig. 5: 800) that has a first main surface on one side and a second main surface on the other side (please see par. 84 and fig. 5 surfaces 801 and 802);
a step of forming a main surface electrode (fig. 9: 890b) on the first main surface;
a step of forming a terminal electrode (fig. 10: 8951) on the main surface electrode (please see fig. 10);
a step of forming a sealing insulator (fig. 14: 822) that covers a periphery of the terminal electrode on the first main surface such as to expose a part of the terminal electrode (please see fig. 14); and
a step of cutting the wafer source in a horizontal direction along the first main surface from an intermediate portion of a thickness range of the wafer source (par. 100 teaches cutting the sealed package), and
separating the wafer source into a sealed wafer on the sealing insulator side and an unsealed wafer on the second surface side (please see fig. 17-20).
Regarding claim 2, YANAGIDA teaches a manufacturing method for the semiconductor device according to claim 1, wherein the separating step of the wafer source includes a step of cutting out the sealed wafer that is thinner than the sealing insulator (please see fig. 17).
Regarding claim 3, YANAGIDA teaches a manufacturing method for the semiconductor device according to claim 1, wherein the separating step of the wafer source includes a step of cutting out the unsealed wafer that is thicker than the sealed wafer (please see fig. 17).
Regarding claim 10, YANAGIDA teaches a manufacturing method for the semiconductor device according to claim 1, wherein the wafer source includes a monocrystal of a wide bandgap semiconductor (par. 84).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-20 allowed.
The following is an examiner’s statement of reasons for allowance: prior art fails to teach, at least, the temporal ordering of method steps outlined in claim 11. Claims 12-20 are objected to based on their dependency of claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818
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