DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Amendment
Acknowledgment is made of applicant's Amendment, filed 11-24-2025. The changes and remarks disclosed therein have been considered.
Claim(s) 1 and 8-11 has/have been amended, claim(s) 7 has/have been cancelled, claim(s) 1-6 and 8-11 remain(s) pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 10 recite(s) the language (emphasis added) “when a voltage applied to the transmission gate from one of the first power source and the second power source through one of the first phase change memory element and the second phase change memory element is referred to as a first polarity voltage and a voltage applied from the transmission gate through one of the first phase change memory element and the second phase change memory element to one of the first power source and the second power source is referred to as a second polarity voltage”, where “a voltage” is recited twice and it is unclear if the voltages are the same. Examiner suggests adding an adjective such as --first-- or --second-- for different recitations of “a voltage” if they are different.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8, 10, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anaashari, US 10056907 B1.
As to claim 1, Anaashari discloses a configuration bit circuit (see Anaashari Fig 1) for a programmable logic device (see Anaashari Col 3 Lines 13-29) comprising:
a first phase change memory element (see Anaashari Fig 1 Ref 104A and Col 11 Lines 47-58) and a second phase change memory element (see Anaashari Fig 1 Ref 104B) connected in series between a first power source (see Anaashari Fig 1 Ref Vcc) and a second power source (see Anaashari Fig 1 Ref Vss); a first selection element (see Anaashari Fig 1 and Fig 4 Ref 402) connected to the first phase change memory element and the second phase change memory element in a first direction (see Anaashari annotated Fig 1 below); and a CMOS inverter (see Anaashari Fig 12 Ref 1212; The disclosed latch is comprised of CMOS inverters.) connected to the first phase change memory element and the second phase change memory element in a second direction (see Anaashari annotated Fig 1 below) and the CMOS inverter disposed between a third power source (see Anaashari Fig 13 Ref VDD) and a fourth power source (see Anaashari Fig 13 ground symbol below Ref 1316C), wherein
a voltage of the first power source or the second power source is lower than (see Anaashari Col 27 Lines 13-28, Fig 3A Ref HIGH RESISTANCE, and Fig 3B Ref HIGH RESISTANCE; Ground voltage is lower than the thresholds of the disclosed resistive elements.) a threshold voltage when the first phase change memory element and the second phase change memory element are in a high resistance state (see Anaashari Cols 14-16 Lines 6-29).
As to claim 2, Anaashari discloses the configuration bit circuit according to claim 1, wherein
the first selection element is a transistor (see Anaashari Fig 1 and Fig 4 Ref 402).
As to claim 3, Anaashari discloses the configuration bit circuit according to claim 1, wherein
the first selection element is a transmission gate (see Anaashari Fig 1, Fig 4 Ref 402, and Col 18 Lines 21-31).
As to claim 8, Anaashari discloses the configuration bit according to claim 1, wherein the voltage of the first power source or second power source is higher than a threshold voltage of an NMOS transistor included in the CMOS inverter (see Anaashari Col 27 Lines 13-50).
As to claim 10, Anaashari discloses a method of programming a configuration bit circuit (see Anaashari Fig 1) for the programmable logic device (see Anaashari Col 3 Lines 13-29), the configuration bit circuit including:
a first phase change memory element (see Anaashari Fig 1 Ref 104A and Col 11 Lines 47-58), and a second phase change memory element (see Anaashari Fig 1 Ref 104B) connected in series between a first power source (see Anaashari Fig 1 Ref Vcc) and a second power source (see Anaashari Fig 1 Ref Vss); a first selection element (see Anaashari Fig 1 and Fig 4 Ref 402) connected to the first phase change memory element and second phase change memory element in a first direction (see Anaashari annotated Fig 1 above); and a CMOS inverter (see Anaashari Fig 12 Ref 1212; The disclosed latch is comprised of CMOS inverters.) connected to the first phase change memory element and second phase change memory element in a second direction (see Anaashari annotated Fig 1 above) and disposed between a third power source (see Anaashari Fig 13 Ref VDD) and a fourth power source (see Anaashari Fig 13 ground symbol below Ref 1316C), wherein
a voltage of the first power source or the second power source is lower than (see Anaashari Col 27 Lines 13-28, Fig 3A Ref HIGH RESISTANCE, and Fig 3B Ref HIGH RESISTANCE; Ground voltage is lower than the thresholds of the disclosed resistive elements.) a threshold voltage when the first phase change memory element and second phase change memory element are in a high resistance state (see Anaashari Cols 14-16 Lines 6-29); and
the method comprising:
when a voltage applied to the transmission gate from one of the first power source and the second power source through one of the first phase change memory element and the second phase change memory element is referred to as a first polarity voltage (see Anaashari Cols 14-16 Lines 6-29) and a voltage applied from the transmission gate through one of the first phase change memory element and the second phase change memory element to one of the first power source and the second power source is referred to as a second polarity voltage (see Anaashari Cols 14-16 Lines 6-29), programming one of the first phase change memory element and the second phase change memory element to be in a first resistance state by the first polarity voltage (see Anaashari Cols 14-16 Lines 6-29); and programming one of the first phase change memory element and the second phase change memory element to be in a second resistance state by the second polarity voltage (see Anaashari Cols 14-16 Lines 6-29), wherein
one of the first phase change memory element and the second phase change memory element is in the first resistance state and the other is in the second resistance state, one of the first resistance state and the second resistance state refers to a low resistance state because the phase change memory element is in a crystalline phase, and the other refers to a high resistance state because the phase change memory element is in an amorphous phase (see Anaashari Cols 14-16 Lines 6-29).
As to claim 11, Anaashari discloses a programmable logic device (see Anaashari Col 3 Lines 13-29) including a configuration bit circuit (see Anaashari Fig 1), the configuration bit circuit comprising:
a first phase change memory element (see Anaashari Fig 1 Ref 104A and Col 11 Lines 47-58) and a second phase change memory element (see Anaashari Fig 1 Ref 104B) connected in series between a first power source (see Anaashari Fig 1 Ref Vcc) and a second power source (see Anaashari Fig 1 Ref Vss); a first selection element (see Anaashari Fig 1 and Fig 4 Ref 402) connected to the first phase change memory element and the second phase change memory element in a first direction (see Anaashari annotated Fig 1 above); and a CMOS inverter (see Anaashari Fig 12 Ref 1212; The disclosed latch is comprised of CMOS inverters.) connected to the first phase change memory element and the second phase change memory element in a second direction (see Anaashari annotated Fig 1 above) and disposed between a third power source (see Anaashari Fig 13 Ref VDD) and a fourth power source (see Anaashari Fig 13 ground symbol below Ref 1316C), wherein
a voltage of the first power source or the second power source is lower than (see Anaashari Col 27 Lines 13-28, Fig 3A Ref HIGH RESISTANCE, and Fig 3B Ref HIGH RESISTANCE; Ground voltage is lower than the thresholds of the disclosed resistive elements.) a threshold voltage when the first phase change memory element and the second phase change memory element are in a high resistance state (see Anaashari Cols 14-16 Lines 6-29).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anaashari, US 10056907 B1, in view of Tortorelli, US 20200372966 A1.
As to claim 4, Anaashari discloses the configuration bit circuit according to claim 1, wherein
the first selection element is a three-terminal switching element.
Tortorelli a two-terminal switching element discloses a two-terminal switching element (see Tortorelli Fig 2 Ref 215 and Para [0054]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a configuration bit circuit, may implement a particular selector, as disclosed by Tortorelli. The inventions are well known variants of circuit which can implemented in FPGAs and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Tortorelli’s attempt to reduce bias across unselected elements (see Tortorelli Para [0055]).
As to claim 5, Anaashari and Tortorelli disclose the configuration bit circuit according to claim 4, wherein
the two-terminal switching element is any one of an ovonic threshold switch, a transition metal oxide switch, a MIEC switch, a complementary resistance switch, and doped amorphous silicon (see Tortorelli Fig 2 Ref 215 and Para [0054]).
As to claim 6, Anaashari discloses the configuration bit circuit according to claim 1, wherein
filamentary memory element.
Anaashari does not appear to disclose
a phase change layer of the first phase change memory element and the second phase change memory element includes Ge, Sb, and Te, and with Ge<50 at %, Sb<40 at %, and Te≥50 at % at an atomic ratio.
Tortorelli discloses a phase change layer of the first phase change memory element and second phase change memory element includes Ge, Sb, and Te, and may be Ge<50 at %, Sb<40 at %, and Te≥50 at % at an atomic ratio (see Tortorelli Para [0059]; Examiner takes notice that 225 GST is a commonly used programmable resistive material that has the claimed chemical composition.).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a configuration bit circuit, may implement a programable element, as disclosed by Tortorelli. The inventions are well known variants of circuit which can implemented in FPGAs and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Tortorelli’s attempt to engineer a large margin between high and lower resistance (see Tortorelli Para [0060]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anaashari, US 10056907 B1, in view of Onkaraiah, US 10566055 B2.
As to claim 9, Anaashari discloses the configuration bit circuit according to claim 1, wherein
the voltage applied of the first power source or second power source has a relation to a voltage applied to the third power source or the fourth power source (see Anaashari Fig 13 Ref VDD; Examiner takes notice that 5V is a common high rail for CMOS microelectronics.).
Anaashari does not appear to disclose is 0.5 times or less than a voltage applied.
Onkaraiah discloses 0.5 times or less than a voltage applied (see Onkaraiah Cols 8-9 Lines 57-16 and Fig 7 the inverter right of Ref 304.1).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a method, may be implemented with a particular voltage, as disclosed by Onkaraiah. The inventions are well known variants of circuit which can implemented in FPGAs and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Onkaraiah’s attempt to simplify switching circuity for programming data (see Onkaraiah Col 1 Lines 18-29).
Response to Arguments
Applicant's arguments filed 11/24/2025 have been fully considered but they are not persuasive.
The scope of the limitations argued are not the same as of that claimed, and the prior art of record reads on the claims given broadest reasonable interpretation. The limitation “a threshold voltage” is not assigned to a particular electronic element of the disclosed circuit, thus there is an element in the circuit where ground voltage is lower than said element’s threshold i.e. a NMOS transistor. The first and second phase change elements are not required to be in the high resistance state at the same time.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 01/14/2026