Prosecution Insights
Last updated: August 16, 2026
Application No. 18/653,101

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
May 02, 2024
Priority
Nov 01, 2023 — RE 10-2023-0149046
Examiner
GREEN, TELLY D
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
1070 granted / 1307 resolved
+21.9% vs TC avg
Minimal +4% lift
Without
With
+3.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
59 currently pending
Career history
1360
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
56.1%
+16.1% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
12.4%
-27.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1307 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, Species 1, Sub-species A, claims 1-12. in the reply filed on July 27, 2026 is acknowledged. Claims 13-20 have been withdrawn. Action on the merits is as follows: Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 recites “an upper surface of the separation structure and the upper surface of each of the plurality of gate contact parts are positioned at substantially the same distance from an upper surface of the substrate”. Claim 12 recites “side surfaces of the plurality of interlayer insulation layers and side surfaces of the plurality of gate electrodes are substantially coplanar”. These claimed features are either the same distance (claim 3) or (horizontally or vertically) coplanar (claim 12). The TERM, ‘Substantially’ The term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as "being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how much the value can deviate from “the same distance of the substrate” or being (horizontally or vertically) coplanar. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (in this case, the distance from substrate and being coplanar), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. For the purpose of examination the Examiner is taking these recitations as ‘positioned at the same distance” and “are coplanar”. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 and 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Lee) (US 2022/0320515 A1) in view of Tang (US 20200251487 A1). In regards to claim 1, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) discloses a semiconductor device (Figs. 2A, 11A, items 1, 200) comprising: a substrate (item 17 or 4) comprising a cell array region (item MCA) and a contact region (item SA); a gate stacking structure (items 21’, 35’) including a plurality of interlayer insulation layers (items 25, 38) and a plurality of gate electrodes (items 27g, 40g) which are alternately stacked on the substrate (item 17 or 4); a channel structure (item 47) penetrating the gate stacking structure (items 21’, 35’)in the cell array region (item MCA); an upper insulation layer (item 32, 44 or 32 plus 44) covering the gate stacking structure (items 21’, 35’) and the channel structure (item 47); and a plurality of gate contact parts (item 89) penetrating the upper insulation layer (item 32, 44 or 32 plus 44) and connected to the plurality of gate electrodes (items 27g, 40g) in the contact region (item SA), wherein at least a part of some of the plurality of gate contact parts (item 89) penetrates at least one passing gate electrode (items 27g, 40g) among the plurality of gate electrodes (items 27g, 40g) and integrates with a connection gate electrode (items 27g, 40g), of the plurality of gate electrodes (items 27g, 40g), positioned under the at least on passing gate electrode (items 27g, 40g), but does not specifically disclose at least a part of an upper surface of the upper insulation layer (item 32, 44 or 32 plus 44) has a concave shape protruding toward the substrate. Tang (Figs. 1A-2, 3G and associated text) discloses at least a part of an upper surface of the upper insulation layer (shown but not labeled insulating layer, item 122 or shown but not labeled insulating layer plus item 122) has a concave shape (shown but not labeled) protruding toward the substrate (item 102). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Tang for the purpose of protection and increasing the conductor layer planarization window to solve conductor residual issues (paragraph 30). In regards to claim 2, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) discloses further comprising: a separation structure (item 77) penetrating the gate stacking structure (items 21’, 35’) in the cell array region (item MCA), wherein a maximum width of the separation structure (item 77) is narrower than a maximum width of each of the plurality of gate contact parts (item 89). In regards to claim 3, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) discloses wherein: an upper surface of the separation structure (item 77) and the upper surface of each of the plurality of gate contact parts (item 89) are positioned at substantially the same distance from an upper surface of the substrate (item 17 or 4). In regards to claim 8, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) as modified by Tang (Figs. 1A-2, 3G and associated text) discloses: the upper insulation layer (shown but not labeled insulating layer, item 122 or shown but not labeled insulating layer plus item 122) comprises: a first recess part having a concave shape (shown but not labeled) protruding toward the substrate in the contact region, wherein an upper surface in the center of the first recess part is positioned closer to an upper surface of the substrate (item 102) than an upper surface of each of the plurality of gate contact parts (item128). In regards to claim 9, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) as modified by Tang (Figs. 1A-2, 3G and associated text) does not specifically disclose the upper insulation layer further comprises: a second recess part having a concave shape protruding toward the substrate in the cell array region, and wherein a bottom surface of the first recess part is positioned farther from the upper surface of the substrate than a bottom surface of the second recess part. It would have been obvious to modify the invention to include a second recess, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193 USPQ 8). It would have been obvious to modify the invention to include a bottom surface of the first recess part being positioned farther from the upper surface of the substrate than a bottom surface of the second recess part, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). In regards to claim 10, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) as modified by Tang (Figs. 1A-2, 3G and associated text) does not specifically disclose wherein: a curvature of the second recess part is less than a curvature of the first recess part. It would have been obvious to modify the invention to include a curvature of the second recess part being less than a curvature of the first recess part, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). In regards to claim 11, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) discloses wherein: the plurality of gate contact parts (item 89) includes a same material as that of the plurality of gate electrodes (items 27g, 40g, paragraph 52), and a thickness of each of the plurality of gate contact parts (item 89) is greater than or equal to a thickness of the plurality of gate electrodes (items 27g, 40g) in the one direction. In regards to claim 12, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) discloses wherein: side surfaces of the plurality of interlayer insulation layers (items 25, 38) and side surfaces of the plurality of gate electrodes (items 27g, 40g) are substantially coplanar. Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Lee) (US 2022/0320515 A1) in view of Tang (US 20200251487 A1) as applied to claims 1-3 above and further in view of Izumi et al. (Izumi) (US 2016/0093524 A1). In regards to claim 4, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) as modified by Tang does not specifically disclose a gate spacer at least partially surrounding each of the plurality of gate contact parts. Izumi (paragraph 84, Fig. 17 and associated text) discloses a gate spacer (item 64) at least partially surrounding each of the plurality of gate contact parts (item 66). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Izumi for the purpose of insulation (paragraph 84). Lee as modified by Tang and Izumi does not specifically disclose wherein the separation structure (item 77, Lee) has a same material as that of the gate spacer (item 64). It would have been obvious to modify the invention to include a separation structure and a gate spacer having a same material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416). In regards to claim 5, Lee (Figs. 2A, 2B, 2C, 11A, 14 and associated text) as modified by Tang and Izumi (paragraph 84, Fig. 17 and associated text) discloses a gate spacer (item 64) at least partially surrounding each of the plurality of gate contact parts (item 66), wherein a bottom surface of the gate spacer (item 64) contacts is disposed on the connection gate electrode (item 46). In regards to claim 6, Lee as modified by Tang and Izumi (paragraph 84, Fig. 17 and associated text) discloses wherein: the gate spacer (item 64) comprises at least one of AlN, AIO, SiOC, SiOCN, SiCN, or High-K materials (paragraph 83). In regards to claim 7, Lee as modified by Tang and Izumi (paragraph 84, Fig. 17 and associated text) discloses wherein: a thickness of the gate spacer (item 64) is about 1/12.sup.th to about ⅛.sup.th of the thickness of each of the plurality of gate contact parts (item 66). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TELLY D. GREEN Examiner Art Unit 2898 /TELLY D GREEN/Primary Examiner, Art Unit 2898 August 4, 2026
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Prosecution Timeline

May 02, 2024
Application Filed
Aug 06, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
86%
With Interview (+3.9%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1307 resolved cases by this examiner. Grant probability derived from career allowance rate.

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