CTNF 18/653,116 CTNF 81546 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-3, 7, 9, 11, and 14-16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sakai et al, US Patent Application Publication 2017/0125359 Regarding claim 1, Sasaki teaches a semiconductor package comprising: a first substrate 310 ; a bridge chip 320 disposed on the first substrate and having a first region 320b and a second region 320a ; an upper semiconductor chip 330 disposed on the first region of the bridge chip; and conductive posts 380 disposed on the second region of the bridge chip and spaced apart from the upper semiconductor chip, wherein the upper semiconductor chip is electrically connected to the conductive posts through the bridge chip ( via wiring layer 322, figure 25 ). Regarding claim 2, Sasaki teaches the bridge chip comprises: first connection pads 325a disposed on an upper surface of the bridge chip and in the first region; second connection pads 325 disposed on the upper surface of the bridge chip and in the second region; and connection structures ( wiring layers in 322 ) disposed in the bridge chip and electrically connected to the first connection pads and the second connection pads, wherein the upper semiconductor chip is electrically connected to the conductive posts through the connection structures ( figure 25 ). Regarding claim 3, Sasaki teaches chip pads of the upper semiconductor chip are respectively electrically connected to the first connection pads, and the conductive posts are respectively disposed on the second connection pads ( figure 25 ). Regarding claim 7, Sasaki teaches a lower semiconductor chip 620A disposed on the first substrate and spaced apart from the bridge chip, wherein the upper semiconductor chip is disposed on a portion of the lower semiconductor chip and spaced apart from another portion of the lower semiconductor chip ( figure 25 ). Regarding claim 9, Sasaki teaches the conductive posts transmit an electrical signal of the upper semiconductor chip, and the interconnection structures receive a voltage (figure 25). Regarding claim 11, Sasaki teaches a semiconductor package comprising: a first substrate 310 ; a first semiconductor chip 620A disposed on the first substrate; a bridge chip 320 disposed on the first substrate and spaced apart from the first semiconductor chip; a second semiconductor chip 330 disposed on a first region 320a of the bridge chip and the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the bridge chip and the first semiconductor chip; and a conductive post 380 disposed on a second region 320b of the bridge chip and spaced apart from the second semiconductor chip, wherein the conductive post is electrically connected to the bridge chip ( via wiring layer 322, figure 25 ). Regarding claim 14, Sasaki teaches the second semiconductor chip is bonded to the first semiconductor chip, and the second semiconductor chip is bonded to the bridge chip ( figure 25 ). Regarding claim 15, Sasaki teaches first upper bumps 670 disposed between the first semiconductor chip and the second semiconductor chip and electrically connected to the first semiconductor chip and the second semiconductor chip; and second upper bumps 332 or 325a disposed between the bridge chip and the second semiconductor chip and electrically connected to the bridge chip and the second semiconductor chip ( figure 25 ). Regarding claim 16, Sasaki teaches the bridge chip comprises: a base substrate 321 ; a bridge insulating layer 322 disposed on the base substrate; a first connection pad 325a disposed on the bridge insulating layer and electrically connected to a chip pad of the second semiconductor chip; a second connection pad 323 disposed on the bridge insulating layer and spaced apart from the first connection pad; and a connection structure (wiring structures in 322) disposed in the bridge insulating layer and electrically connected to the first connection pad and the second connection pad, and the conductive post is disposed on the second connection pad and is electrically connected to the second connection pad ( figure 25 ) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki as applied to claim 1 above, and further in view of Sung et al, US Patent Application Publication 2020/0273799 . Regarding claim 4, Sasaki fails to teach a second substrate disposed on the conductive posts and the upper semiconductor chip; and an upper package disposed on the second substrate, wherein the upper semiconductor chip is electrically connected to the upper package through the conductive posts. However, Sung teaches a second substrate SP2 disposed on the conductive posts 530 or 535 and the upper semiconductor chip 400 ; and an upper package 250 disposed on the second substrate, wherein the upper semiconductor chip is electrically connected to the upper package through the conductive posts ( figure 1 ) by teaching a completes system-in-packages (SIPs), which contain multiple semiconductor dies. The usage of multiple semiconductor dies allow for data at a high speed with a multi-functional operation, thereby improving the electrical device formed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sung with that of Sasaki because using multiple SIPs in a electrical device improves the electrical functionality of said component. Regarding claim 5, Sung teaches the upper package overlaps the conductive posts 530 ( figure 1 ). Regarding claim 6, Sasaki and Sung fails to teach the upper package overlaps about 20 % to about 40 % of a planar area of the upper semiconductor chip. However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) . 07-21-aia AIA Claim (s) 8, 10, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al, US Patent Application Publication 2017/0125359 Regarding claim 8, Sasaki fails to teach the interconnection structures 350 disposed on the first substrate and spaced apart from the bridge chip, the conductive posts, and the upper semiconductor chip, wherein a height of the interconnection structures is greater than a height of the conductive posts, a width of the interconnection structures is greater than a width of the conductive posts ( as shown in figure 25, wherein interconnection structure 350 is larger than conductive posts 380 ), but fails to teach a pitch of the interconnection structures is greater than a pitch of the conductive posts. However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 10, Sasaki fails to teach the height of the conductive posts is about 250 μm to about 350 μm, the width of the conductive posts is about 80 μm to about 120 μm, the pitch of the conductive posts is about 100 μm to about 200 μm, and the height of the interconnection structures is about 300 μm to about 400 μm. However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 17, Sasaki fails to teach a vertical gap between an upper surface of the bridge chip and an upper surface of the first substrate is about 95 % to about 105 % of a vertical gap between an upper surface of the first semiconductor chip and an upper surface of a first redistribution substrate However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) . 07-22-aia AIA Claim (s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki as applied to claim 1 above, and further in view of Sung et al, US Patent Application Publication 2020/0273799 and Kim et al, US Patent Application Publication 2016/0013126 . Regarding claim 12, Sasaki fails to teach a second substrate disposed on the conductive post and the second semiconductor chip; an upper package disposed on the second substrate and vertically overlapping the conductive post; and a heat dissipation structure disposed on the second substrate and spaced apart from the upper package. Sung teaches a second substrate SP2 disposed on the conductive post 530 or 535 and the second semiconductor chip 400 ; an upper package 250 disposed on the second substrate and vertically overlapping the conductive post ( figure 1 ) by teaching a completes system-in-packages (SIPs), which contain multiple semiconductor dies. The usage of multiple semiconductor dies allow for data at a high speed with a multi-functional operation, thereby improving the electrical device formed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sung with that of Sasaki because using multiple SIPs in an electrical device improves the electrical functionality of said component. Sasaki and Sung fail to teach a heat dissipation structure disposed on the second substrate and spaced apart from the upper package. However, Kim teaches a heat dissipation structure 400 disposed on the second substrate 200a and spaced apart from the upper package ( solder balls on 200u in figure 5B) . Heat dissipating structures are used to draw heat from the semiconductor packages, thereby preventing degradation of the semiconductor components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with that of Sasaki and Sung because heat dissipating structures are used to draw heat from the semiconductor packages, thereby preventing degradation of the semiconductor components. Regarding claim 13, Kim teaches the heat dissipation structure overlaps the first semiconductor chip and the second semiconductor chip, and the upper package overlaps the second semiconductor chip ( figure 5B, by teaching the heat dissipating structure being over the entire semiconductor device ) 07-21-aia AIA Claim (s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al, US Patent Application Publication 2017/0125359 in view of Sung et al, US Patent Application Publication 2020/0273799 and Kim et al, US Patent Application Publication 2016/0013126 . Regarding claim 18, Sasaki teaches a semiconductor package comprising: a first redistribution substrate 310 ; solder ball terminals 315 disposed on a lower surface of the first redistribution substrate; a first semiconductor chip 620A mounted on the first redistribution substrate and comprising a through-via 624 ; a bridge chip 320 disposed on the first redistribution substrate and spaced apart from the first semiconductor chip, wherein the bridge chip has a first region 320a and a second region 320b ; a second semiconductor chip 330 disposed on the first semiconductor chip and the first region of the bridge chip, wherein the second semiconductor chip is electrically connected to the first semiconductor chip and the bridge chip; conductive posts 380 disposed on the second region of the bridge chip and spaced apart from the first semiconductor chip; interconnection structures 350 disposed on the first redistribution substrate and spaced apart from the bridge chip, the conductive posts, and the second semiconductor chip; a second redistribution substrate 322 disposed and electrically connected to the conductive posts and the interconnection structures; wherein the bridge chip comprises: a base substrate 321 ; a bridge insulating layer 322 disposed on the base substrate; first connection pads 325a disposed on an upper surface of the bridge insulating layer and electrically connected to chip pads of the second semiconductor chip; second connection pads 323 disposed on the upper surface of the bridge insulating layer and spaced apart from the first connection pads; and connection structures (wiring structures in 322) disposed in the bridge insulating layer, wherein the first connection pads are respectively electrically connected to the second connection pads through the connection structures, and the conductive posts are respectively disposed on the second connection pads ( figure 25 ). Sasaki fails to teach a first molding layer disposed on the first redistribution substrate and covering the bridge chip, the first semiconductor chip, the second semiconductor chip, sidewalls of the conductive posts, and sidewalls of the interconnection structures, wherein the second redistribution is on the first molding layer; an upper package disposed on the second redistribution substrate and vertically overlapping the conductive posts; and a heat dissipation structure disposed on the second redistribution substrate, and spaced apart from the semiconductor package, wherein the heat dissipation structure vertically overlaps the second semiconductor chip, wherein the second semiconductor chip is electrically connected to the upper package through the bridge chip, the conductive posts, and the second redistribution substrate. Sung teaches a molding layer 700 formed on the semiconductor components, which is generally-used in the art as a barrier to electrically insulate the semiconductor components from one another. The combination of this teaching of Sung with that of Sasaki meets the limitation of “a first molding layer disposed on the first redistribution substrate and covering the bridge chip, the first semiconductor chip, the second semiconductor chip, sidewalls of the conductive posts, and sidewalls of the interconnection structures; wherein the second redistribution is on the first molding layer”. Further, Sung teaches an upper package SP2 or 250 disposed on the second redistribution substrate and vertically overlapping the conductive posts 530 ; wherein the second semiconductor chip 400 is electrically connected to the upper package through the bridge chip 510 or 505, right , the conductive posts 530 , and the second redistribution substrate 535 ( figure 1 ) by teaching a completes system-in-packages (SIPs), which contain multiple semiconductor dies. The usage of multiple semiconductor dies allow for data at a high speed with a multi-functional operation, thereby improving the electrical device formed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sung with that of Sasaki because using multiple SIPs in an electrical device improves the electrical functionality of said component. Sung and Sasaki fail to teach a heat dissipation structure disposed on the second redistribution substrate, and spaced apart from the semiconductor package, wherein the heat dissipation structure vertically overlaps the second semiconductor chip. Kim teaches a heat dissipation structure 400u disposed on the second redistribution substrate, and spaced apart from the semiconductor package, wherein the heat dissipation structure vertically overlaps the second semiconductor chip ( figure 5B, by teaching the heat dissipating structure being over the entire semiconductor device )Heat dissipating structures are used to draw heat from the semiconductor packages, thereby preventing degradation of the semiconductor components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with that of Sasaki and Sung because heat dissipating structures are used to draw heat from the semiconductor packages, thereby preventing degradation of the semiconductor components. Regarding claim 19, Sung in view of Kim teaches the upper package overlaps SP2 at least a portion of the first semiconductor chip and at least a portion of the bridge chip, the heat dissipation structure overlaps the first semiconductor chip, and the heat dissipation structure comprises at least one of a heat slug, a heat sink, or a heat pipe ( figure 1 ). Regarding claim 20, Sung teaches the first semiconductor chip comprises a logic chip, the second semiconductor chip comprises a different type of logic chip from the first semiconductor chip, and the upper package comprises a package substrate and a third semiconductor chip, wherein the third semiconductor chip comprises a memory chip [ 0021 ]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. QVJ /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/653,116 Page 2 Art Unit: 2899 Application/Control Number: 18/653,116 Page 3 Art Unit: 2899 Application/Control Number: 18/653,116 Page 4 Art Unit: 2899 Application/Control Number: 18/653,116 Page 5 Art Unit: 2899 Application/Control Number: 18/653,116 Page 6 Art Unit: 2899 Application/Control Number: 18/653,116 Page 7 Art Unit: 2899 Application/Control Number: 18/653,116 Page 8 Art Unit: 2899 Application/Control Number: 18/653,116 Page 9 Art Unit: 2899 Application/Control Number: 18/653,116 Page 10 Art Unit: 2899 Application/Control Number: 18/653,116 Page 11 Art Unit: 2899 Application/Control Number: 18/653,116 Page 12 Art Unit: 2899 Application/Control Number: 18/653,116 Page 13 Art Unit: 2899 Application/Control Number: 18/653,116 Page 14 Art Unit: 2899 Application/Control Number: 18/653,116 Page 15 Art Unit: 2899 Application/Control Number: 18/653,116 Page 16 Art Unit: 2899 Application/Control Number: 18/653,116 Page 17 Art Unit: 2899
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