Prosecution Insights
Last updated: October 02, 2026
Application No. 18/653,157

INTEGRATED CIRCUIT MEMORY DEVICES HAVING HIGHLY INTEGRATED MEMORY CELLS THEREIN WITH ENHANCED LANDING PAD STRUCTURES

Non-Final OA §102
Filed
May 02, 2024
Priority
Jul 05, 2023 — RE 10-2023-0087019
Examiner
TRAPANESE, WILLIAM C
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
506 granted / 656 resolved
+17.1% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
13 currently pending
Career history
669
Total Applications
across all art units

Statute-Specific Performance

§101
11.8%
-28.2% vs TC avg
§103
57.1%
+17.1% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
2.6%
-37.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 656 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-4, 14-16 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (hereinafter Lee, US 2023/0055499). In regards to independent claim 1, Lee teaches an integrated circuit memory device, comprising: a substrate(100); a bit line extending in a first horizontal direction on the substrate (Fig. 5B, BL); a channel structure extending on the bit line, the channel structure including a horizontal portion on the bit line and a vertical channel portion extending upwardly from one end of the horizontal portion(Fig. 5B, CP); a word line on the horizontal portion and crossing the bit line to extend in a second horizontal direction, intersecting the first horizontal direction (Fig. 5B, WL1, 2); and a landing pad structure electrically connected to the vertical channel portion, the landing pad structure including a first contact portion in contact with an upper surface of the vertical channel portion and a second contact portion protruding downwardly from a lower surface of the first contact portion (Fig. 5B, LP). In regards to dependent claim 2, Lee teaches the device of claim 1, wherein a horizontal width of the first contact portion is greater than a horizontal width of the vertical channel portion (Fig. 5B, LP). In regards to dependent claim 3, Lee teaches wherein the second contact portion is in contact with a side surface of the vertical channel portion (Fig. 5B, LP). In regards to dependent claim 4, Lee teaches wherein an upper region of the vertical channel portion extends between the second contact portion and the word line (Fig. 5B, LP). In regards to dependent claim 14, Lee teaches: an upper insulating structure covering upper surfaces of the bit line and the word line (Fig. 5B, 155, 165); and wherein the landing pad structure further includes a first protrusion protruding to the upper insulating structure (Fig. 5B, LP).. In regards to dependent claim 15, Lee teaches wherein the landing pad structure further includes a second protrusion protruding from a side surface of the second contact portion in a direction away from the word line (Fig. 5B, LP). In regards to dependent claim 16, Lee teaches wherein the channel structure includes an internal channel structure and an external channel structure extending on the internal channel structure ((Fig. 5B, 155, 153 stack vs VCP); wherein an upper surface of the external channel structure extends on a higher level than an upper surface of the internal channel structure (Fig. 5B, 155, 153, stack).; wherein the first contact portion is in contact with the upper surface of the external channel structure (Fig. 5B, LP , 155).; and wherein the second contact portion is in contact with a side surface of the external channel structure and the upper surface of the internal channel structure (Fig. 5B, LP, VCP).. Allowable Subject Matter Claims 17-20 allowed. Claims 5-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

May 02, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12733518
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
98%
With Interview (+20.9%)
3y 2m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 656 resolved cases by this examiner. Grant probability derived from career allowance rate.

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