DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an Application 05/02/2024.
Currently, claims 1-20 are examined as below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 05/02/2024. The IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Non-Volatile Memory Device with Improved Device Performance and Reliability
(Clean Version) Non-Volatile Memory Device with Improved Device Performance and Reliability
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 is indefinite, because the limitation “a first gate dielectric layer disposed the first gate electrode and the substrate” renders the claim indefinite. It is unclear whether a first gate dielectric layer is disposed on or between the first gate electrode and the substrate. The limitation will be interpreted as a first gate dielectric layer disposed between the first gate electrode and the substrate.
Claim 9 is indefinite, because the limitation “the second gate electrode” in line 6 is not mentioned before. Only “a second gate” is recited earlier in the claim. There is insufficient antecedent basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8, 10-14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0322262 A1 to Li et al. (“Li”) in view of US 2022/0208787 A1 to Baek et al. (“Baek”).
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Regarding independent claim 1, Li in Figs. 1a, 2g and Annotated Fig. 1a teaches a memory device (Fig. 1, ¶ 2 & ¶ 12, high power device integrated with an integrated circuit (IC) and memory device) comprising:
a peripheral circuit 100 (Fig. 1a, ¶ 13, device 100 is an IC) and a memory device (¶ 12-¶ 13, memory device on the same substrate with the IC 100; Fig. 1a, ¶ 12-¶ 13 disclose the memory device would be stacked on the IC 100 as the memory device and the IC 100 share the same substrate 102) that are sequentially stacked, wherein the peripheral circuit 100 comprises:
a substrate 102 (¶ 13, substrate 102) including a device isolation layer 150 (¶ 29-¶ 30, deep trench isolation (DTI) region or structure 150 including silicon oxide) in a device isolation trench 150 (¶ 29, deep trench isolation (DTI) region or structure 150) therein defining an active region 104 (Fig. 1a, ¶ 45, buried layer 104 which is set in the boundary of (i.e., defined by) the trenches 150, and the buried layer 104 is used for electrical connection i.e., the buried layer 104 is a functioning, active region);
a first gate electrode 144 (Fig. 1a, ¶ 19, gate electrode 144 on the left) extending in a first horizontal direction z (Fig. 1a, ¶ 19, z direction, the gate traverses the device region along the z direction) on the active region 104 of the substrate 102;
an insulating pattern 180a (Annotated Fig. 1a, ¶ 18, shallow trench isolation (STI) region 180a) in a first recess 180a (Annotated Figs. 1a, 2g, ¶ 51, the leftmost isolation trench 180a filled with silicon oxide) and a second recess 180b (Annotated Figs. 1a, 2g, ¶ 51, isolation trench 180b filled with silicon oxide in the region 112a) spaced apart in a second horizontal direction x (Fig. 1a, x direction) intersecting the first horizontal direction z (¶ 19) within the active region 104 on opposing sides of the first gate electrode 144 (Fig. 1a);
a first low concentration doped region 106a (¶ 27, first device well 106a, and the device well is a lightly doped region) within the substrate 102 (Fig. 1a) and extending along an outer wall of the first recess 180a (Annotated Fig. 1a);
a second low concentration doped region 112a (¶ 25, drift well 112a is a lightly doped region) within the substrate 102 (Fig. 1a) and extending along an outer wall of the second recess 180b (Annotated Fig. 1a);
a first source/drain region 132a (¶ 21, first doped region or source region 132a) buried in the first low concentration doped region 106a between the first recess 180a and the device isolation trench 150 (Fig. 1a, the center 150) in the second horizontal direction x; and
a second source/drain region 134a (¶ 21, second doped region or drain region 134a) buried in the second low concentration doped region 112a between the second recess 180b and the device isolation trench 150 (Fig. 1a, the center 150) in the second horizontal direction x,
wherein a depth of each of the first recess 180a and the second recess 180b is 2000-5000 Angstrom (¶ 18), which is 200 nm to 500 nm that overlaps the claimed range of 400 nm or less (see Note below), and
wherein a depth of the device isolation trench 150 is 28 μm (¶ 29), which is 28000 nm that anticipates the claimed range of 1000 nm or more but is less than a thickness of the substrate 102 in a vertical direction (Fig. 1a).
Note: “In the case where the claimed ranges 'overlap or lie inside ranges disclosed by the prior art' a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)" (quoting MPEP 2144.05.I.).
Since the depth of each of the first and second recesses being 200 nm to 500 nm taught by Li overlaps with the claimed range, a prima facie case of obviousness exist. The burden shifts to the Applicant to show that the claimed range provides unexpected result that is difference in kind and not difference in degree. See In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Li does not explicitly disclose the memory device is a non-volatile memory device, and the peripheral circuit and a memory cell array that are sequentially stacked.
Baek recognizes a need for providing a semiconductor device of storing a large amount of data in an electronic system requiring data storage (¶ 3) that can suppress a decrease in breakdown voltage and promote an increased current (¶ 4). Baek satisfies the need by providing a non-volatile memory device (¶ 212, ¶ 3, non-volatile memory device including a NAND flash memory device), and a peripheral circuit PCS (Fig. 8, ¶ 46, peripheral circuit structure PCS) and a memory cell array MCA (Fig. 8, ¶ 53, memory cell array MCA) that are sequentially stacked.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the memory device taught by Li with the non-volatile memory device and the structure of non-volatile memory device taught by Baek, so as to provide a semiconductor device of storing a large amount of data in an electronic system requiring data storage (Baek: ¶ 3) that can suppress a decrease in breakdown voltage and promote an increased current (Baek: ¶ 4).
Regarding claim 2, the combination of Li and Baek further teaches the first low concentration doped region 106a (Li) comprises a portion between the first recess 180a and the device isolation trench 150 (Li: Fig. 1a, the leftmost 150); and
the second low concentration doped region 112a comprises a portion between the second recess 180b and the device isolation trench 150 (Li: Annotated Fig. 1a).
Regarding claim 3, the combination of Li and Baek further teaches the first gate electrode 144 (Li) comprises polysilicon (Li: ¶ 19).
Regarding claim 4, the combination of Li and Baek further teaches a first gate dielectric layer 142 (Li: Fig. 1a, ¶ 19, gate dielectric 142) disposed the first gate electrode 144 and the substrate 102.
Regarding claim 5, the combination of Li and Baek further teaches a first source/drain contact 176 (Li: ¶ 36, contact 176) on the first source/drain doped region 132a (Li: Fig. 1a) and configured to apply a voltage to the first source/drain region 132a (see Note below); and
a second source/drain contact 176 (Li: ¶ 36, contact 176) on the second source/drain doped region 134a (Li: Fig. 1a) and configured to apply a voltage to the second source/drain region 134a (see Note below).
Note: Limitations of "configured to apply a voltage to the first source/drain region" and “configured to apply a voltage to the second source/drain region” are attempting to define the claimed first source/drain contact and second source/drain contact by what they do, rather than by what they are, which can be evidenced by their specific structures or specific compositions. See MPEP § 2173.05(g). The limitations can be construed as a function and/or a property of the claimed non-volatile memory device.
According to Section 2114 of the MPEP, "While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) (The absence of a disclosure in a prior art reference relating to function did not defeat the Board’s finding of anticipation of claimed apparatus because the limitations at issue were found to be inherent in the prior art reference); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original)".
Here, since the combination of Li and Baek teaches all of the claimed structure limitations of the claimed non-volatile memory device, the non-volatile memory device taught by Li and Baek is capable of performing the claimed function as recited in the limitation above.
Furthermore, according to Section 2112.III of the MPEP, "Where applicant claims a composition in terms of a function, property or characteristic{,} and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103, expressed as a 102/103 rejection. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic. Therefore, a 35 U.S.C. 102/103 rejection is appropriate for these types of claims as well as for composition claims {underlined for emphasis}."
Here, the limitations do not structurally distinguish the claimed first source/drain contact and the claimed second source/drain contact over the prior art as are they directed to a function or property of the claimed non-volatile memory device. The non-volatile memory device including inherently has the property or can function as recited in the limitation above.
Regarding claim 8, the combination of Li and Baek does not explicitly disclose the first recess and the device isolation trench have a same width in the second horizontal direction.
However, it would have been obvious to form the widths within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 10, the combination of Li and Baek further teaches the outer wall of the first recess 180a (Li: Annotated Fig. 1a) comprises a first outer wall and a second outer wall, which are opposite to one another in the second horizontal direction x (Li: Annotated Fig. 1a), and wherein the first low concentration doped region 106a surrounds the first outer wall and the second outer wall (Li: Annotated Fig. 1a).
Regarding independent claim 11, Li in Figs. 1a, 2e, 2g and Annotated Fig. 1a teaches a memory device (Fig. 1, ¶ 2 & ¶ 12, high power device integrated with an integrated circuit (IC) and memory device) comprising:
a peripheral circuit 100 (Fig. 1a, ¶ 13, device 100 is an IC) comprising a plurality of transistors 140a, 140b (¶ 16, first polarity type lateral double-diffused metal oxide semiconductor (LDMOS) transistor 140a and second polarity type LDMOS transistor 140b), wherein the plurality of transistors 140a, 140b comprise:
a pair of gate electrodes 144 (Fig. 1a, ¶ 19, gate electrodes 144) extending in a first horizontal direction z (Fig. 1a, ¶ 19, z direction) on an active region 104 (Fig. 1a, ¶ 45, buried layer 104 is used for electrical connection i.e., the buried layer 104 is a functioning, active region, and the region 104 is set in the boundary of (i.e., defined by) the trenches 150) defined by a device isolation layer 150 (¶ 29, deep trench isolation (DTI) region or structure 150) in a substrate 102 (Fig. 1a, ¶ 13, substrate 102) and spaced apart from each other in a second horizontal direction x (Fig. 1a, x direction) intersecting the first horizontal direction z (Fig. 1a, ¶ 19);
a plurality of low concentration doped regions 106a, 106b, 112a, 112b (Fig. 1a, ¶ 27, first device well 106a, second device well 106b, in which the device wells are lightly doped regions; ¶ 25, drift wells 112a, 112b are lightly doped regions) respectively extending in the substrate 102 along outer walls of a plurality of recesses 180a-180d (Annotated Figs. 1a, 2g, ¶ 51, isolation trenches 180a-180d filled with silicon oxide) on opposing sides of each of the pair of gate electrodes 144 (Annotated Fig. 1a); and
a plurality of source/drain regions 132a, 134a, 132b, 134b (Fig. 1a, ¶ 21, first doped regions or source regions 132a, 132b, and second doped regions or drain regions 134a, 134b) buried in the plurality of low concentration doped regions 106a, 106b, 112a, 112b (Fig. 1a),
wherein the device isolation layer 150 is in a device isolation trench 150 or 251 (Figs. 1a, 2e, ¶ 29, ¶ 44, deep trench isolation (DTI) region or structure 150, or deep isolation trenches 251 for accommodating the layer 150) extending around the pair of gate electrodes 144 (Fig. 1a),
wherein a depth of each of the plurality of recesses 180a-180d is 2000-5000 Angstrom (¶ 18), which is 200 nm to 500 nm that overlaps the claimed range of 400 nm or less (see Note below), and
wherein a depth of the device isolation trench 150 is 28 μm (¶ 29), which is 28000 nm that anticipates the claimed range of 1000 nm or more but is less than a thickness of the substrate 102 in a vertical direction (Fig. 1a).
Note: “In the case where the claimed ranges 'overlap or lie inside ranges disclosed by the prior art' a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)" (quoting MPEP 2144.05.I.).
Since the depth of each of the first and second recesses being 200 nm to 500 nm taught by Li overlaps with the claimed range, a prima facie case of obviousness exist. The burden shifts to the Applicant to show that the claimed range provides unexpected result that is difference in kind and not difference in degree. See In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Li does not explicitly disclose the memory device is a non-volatile memory device.
Baek recognizes a need for providing a semiconductor device of storing a large amount of data in an electronic system requiring data storage (¶ 3). Baek satisfies the need by providing a non-volatile memory device (¶ 212, ¶ 3, non-volatile memory device including a NAND flash memory device).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the memory device taught by Li with the non-volatile memory device taught by Baek, so as to provide a semiconductor device of storing a large amount of data in an electronic system requiring data storage (Baek: ¶ 3).
Regarding claim 12, the combination of Li and Baek further teaches each of the pair of gate electrodes 144 comprises polysilicon (Li: ¶ 19).
Regarding claim 13, the combination of Li and Baek further teaches the pair of gate electrodes 144 comprises a first gate electrode 144 (Li: Fig. 1a, ¶ 19, gate electrode 144) and a second gate electrode 144 (Li: Fig. 1a, ¶ 19, gate electrode 144), and
wherein the plurality of low concentration doped regions 106a, 106b, 112a, 112b comprise:
a first low concentration doped region 106a (Li: Fig. 1a, ¶ 27, first device well 106a, in which the device well is lightly doped region) in the active region 104 between the device isolation trench 150 and the first gate electrode 144;
a second low concentration doped region 112a (Li: Fig. 1a, ¶ 25, drift well 112a is lightly doped region) in the active region 104 between the first gate electrode 144 and the second gate electrode 144; and
a third low concentration doped region 106b (Li: Fig. 1a, ¶ 27, second device well 106b, in which the device well is lightly doped region) in the active region 104 between the second gate electrode 144 and the device isolation trench 150.
Regarding claim 14, the combination of Li and Baek further teaches the plurality of recesses 180a-180d comprise a first recess 180a (Li: Annotated Figs. 1a, 2g, ¶ 51, isolation trench 180a filled with silicon oxide), a second recess 180b (Li: Annotated Figs. 1a, 2g, ¶ 51, isolation trench 180b filled with silicon oxide), a third recess 180c (Li: Annotated Figs. 1a, 2g, ¶ 51, isolation trench 180c filled with silicon oxide), and a fourth recess 180d (Li: Annotated Figs. 1a, 2g, ¶ 51, isolation trench 180d filled with silicon oxide) spaced apart from each other in the second horizontal direction x (Li: Annotated Fig. 1a), and
wherein the plurality of source/drain regions 132a, 134a, 132b, 134b comprise:
a first source/drain region 132a (Li: Fig. 1a, ¶ 21, first doped region or source region 132a) buried in the first low concentration doped region 106a between the first recess 180a and the device isolation trench 150 (Fig. 1a, the center 150);
a second source/drain region 134a (Li: Fig. 1a, ¶ 21, second doped region or drain region 134a) buried in the second low concentration doped region 112a between the second recess 180b and the third recess 180c (Li: Annotated Fig. 1a); and
a third source/drain region 132b (Li: Fig. 1a, ¶ 21, first doped region or source region 132b) buried in the third low concentration doped region 106b between the fourth recess 180d and the device isolation trench 150 (Fig. 1a, the center 150).
Regarding claim 18, the combination of Li and Baek further teaches a plurality of insulating patterns 180a-180d (Li: Annotated Fig. 1a, ¶ 18, shallow trench isolation (STI) regions 180a-180d) respectively provided inside the plurality of recesses 180a-180d,
wherein the plurality of insulating patterns 180a-180d each include oxide (Li: ¶ 51, silicon oxide).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 6-7 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 6 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 6, the first low concentration doped region and the second low concentration doped region each comprises a first conductivity type of impurities having a first concentration.
Claim 7 would be allowable, because claim 7 depends from the allowable claim 6.
Claim 15 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 15, wherein the second source/drain region is shared by a first transistor and a second transistor defined by the first gate electrode and the second gate electrode.
Claim 16 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 16, the first low concentration doped region, the second low concentration doped region, and the third low concentration doped region each comprise a first conductivity type of impurities having a first concentration; the first source/drain region, the second source/drain region, and the third source/drain region comprise the first conductivity type of impurities having a second concentration greater than the first concentration.
Claim 17 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 17, wherein the source/drain contact is shared by a first transistor and a second transistor defined by the first gate electrode and the second gate electrode.
Claim 9 is rejected, but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 9 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 9, wherein the second low concentration doped region further includes a portion in the substrate extending along an outer wall of the third recess, and wherein the second source/drain region is between the second recess and the third recess and is shared by a first transistor and a second transistor defined by the first gate electrode and the second gate electrode.
Claims 19-20 are allowed.
Regarding independent claim 19, Li in Figs. 1a, 2g, and Annotated Fig. 1a teaches a memory device (Fig. 1, ¶ 2 & ¶ 12, high power device integrated with an integrated circuit (IC) and memory device) comprising:
a peripheral circuit 100 (Fig. 1a, ¶ 13, device 100 is an IC) comprising a plurality of transistors 140a, 140b (¶ 16, first polarity type lateral double-diffused metal oxide semiconductor (LDMOS) transistor 140a and second polarity type LDMOS transistor 140b) provided on a substrate 102 (Fig. 1a, ¶ 13, substrate 102); and
wherein the plurality of transistors 140a, 140b comprise:
a first polysilicon electrode 144 (Fig. 1a, ¶ 19, gate electrodes 144 is polysilicon) and a second polysilicon electrode 144 (Fig. 1a, ¶ 19, gate electrodes 144 is polysilicon) extending in a first horizontal direction z (Fig. 1a, ¶ 19, z direction) on an active region 104 (Fig. 1a, ¶ 45, buried layer 104 is used for electrical connection i.e., the buried layer 104 is a functioning, active region, and the region 104 is set in the boundary of (i.e., defined by) the trenches 150) defined by a device isolation layer 150 (Fig. 1a, ¶ 29, deep trench isolation (DTI) region or structure 150) in the substrate 102 and spaced apart from each other in a second horizontal direction x (Fig. 1a, x direction) intersecting the first horizontal direction z (Fig. 1a, ¶ 19);
a plurality of low concentration doped regions 106a, 106b, 112a, 112b (Fig. 1a, ¶ 27, first device well 106a, second device well 106b, in which the device wells are lightly doped regions; ¶ 25, drift wells 112a, 112b are lightly doped regions) respectively provided in the substrate 102 along outer walls of a plurality of recesses 180a-180d (Annotated Figs. 1a, 2g, ¶ 51, isolation trenches 180a-180d filled with silicon oxide) on opposing sides of each of the first polysilicon electrode 144 and the second polysilicon electrode 144; and
a plurality of source/drain regions 132a, 134a, 132b, 134b (Fig. 1a, ¶ 21, first doped regions or source regions 132a, 132b, and second doped regions or drain regions 134a, 134b) buried in the plurality of low concentration doped regions 106a, 106b, 112a, 112b,
wherein the device isolation layer 150 is in a device isolation trench 150 or 251 (Figs. 1a, 2e, ¶ 29, ¶ 44, deep trench isolation (DTI) region or structure 150, or deep isolation trenches 251 for accommodating the layer 150) extending around the first and second polysilicon electrodes 144,
wherein the plurality of low concentration doped regions 106a, 106b, 112a, 112b comprise:
a first low concentration doped region 106a (Fig. 1a, ¶ 27, first device well 106a, in which the device well is lightly doped region) between the device isolation trench 150 and the first polysilicon electrode 144;
a second low concentration doped region 112a (Fig. 1a, ¶ 25, drift well 112a is lightly doped region) between the first polysilicon electrode 144 and the second polysilicon electrode 144; and
a third low concentration doped region 112b (Fig. 1a, ¶ 25, drift well 112b is lightly doped region) spaced apart from the second low concentration doped region 112a with the second polysilicon electrode 144 therebetween,
wherein the plurality of recesses 180a-180d include a first recess 180a (Annotated Figs. 1a, 2g, ¶ 51, isolation trench 180a filled with silicon oxide), a second recess 180b (Annotated Figs. 1a, 2g, ¶ 51, isolation trench 180b filled with silicon oxide), a third recess 180c (Annotated Figs. 1a, 2g, ¶ 51, isolation trench 180c filled with silicon oxide), and a fourth recess 180d (Li: Annotated Figs. 1a, 2g, ¶ 51, isolation trench 180d filled with silicon oxide) spaced apart from each other in the second horizontal direction x (Fig. 1a),
wherein the plurality of source/drain regions 132a, 134a, 132b, 134b comprise:
a first source/drain region 132a (Fig. 1a, ¶ 21, first doped region or source region 132a) buried in the first low concentration doped region 106a;
a second source/drain region 134a (Fig. 1a, ¶ 21, second doped region or drain region 134a) buried in the second low concentration doped region 112a, spaced apart from the first polysilicon electrode 144 with the second recess 180b therebetween (Annotated Fig. 1a), and spaced apart from the second polysilicon electrode 144 with the third recess 180c therebetween (Annotated Fig. 1a); and
a third source/drain region 134b (Fig. 1a, ¶ 21, second doped region or drain region 134b) buried in the third low concentration doped region 112b (Fig. 1a) and spaced apart from the second polysilicon electrode 144 with the fourth recess 180d therebetween (Annotated Fig. 1a),
wherein a depth of each of the plurality of recesses 180a-180d is 2000-5000 Angstrom (¶ 18), which is 200 nm to 500 nm that overlaps the claimed range of 400 nm or less (see Note below), and
wherein a depth of the device isolation trench 150 is 28 μm (¶ 29), which is 28000 nm that anticipates the claimed range of 1000 nm or more but is less than a thickness of the substrate 102 in a vertical direction (Fig. 1a).
Note: “In the case where the claimed ranges 'overlap or lie inside ranges disclosed by the prior art' a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)" (quoting MPEP 2144.05.I.).
Since the depth of each of the first and second recesses being 200 nm to 500 nm taught by Li overlaps with the claimed range, a prima facie case of obviousness exist. The burden shifts to the Applicant to show that the claimed range provides unexpected result that is difference in kind and not difference in degree. See In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Li does not explicitly disclose the memory device is a non-volatile memory device, and a memory cell array configured to be controlled by the peripheral circuit.
Baek recognizes a need for providing a semiconductor device of storing a large amount of data in an electronic system requiring data storage (¶ 3) that can suppress a decrease in breakdown voltage and promote an increased current (¶ 4). Baek satisfies the need by providing a non-volatile memory device (¶ 212, ¶ 3, non-volatile memory device including a NAND flash memory device), and a memory cell array 20 (Fig. 1, ¶ 35, memory cell array 20) configured to be controlled by a peripheral circuit 30 (Fig. 1, ¶ 35, peripheral circuit 30).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the memory device taught by Li with the non-volatile memory device including the memory cell array and the peripheral circuit taught by Baek, so as to provide a semiconductor device of storing a large amount of data in an electronic system requiring data storage (Baek: ¶ 3) that can suppress a decrease in breakdown voltage and promote an increased current (Baek: ¶ 4).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 19, a first source/drain region buried in the first low concentration doped region and spaced apart from the first polysilicon electrode 144 with the first recess therebetween.
Therefore, independent claim 19 is allowed.
Claim 20 is allowed, because claim 20 depends from the allowed claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0028283 A1 to Baek et al. relates to a semiconductor device includes a gate structure disposed on a substrate, in which first impurity region is disposed within an upper portion of the substrate, a third impurity region is within the upper portion of the substrate, a first trench is disposed within the substrate between a first sidewall of the gate structure and the first impurity region, and a first barrier insulation pattern is disposed within the first trench.
US 2024/0304682 A1 to Adachi et al. relates to a semiconductor device includes a semiconductor chip including first and second main surfaces; and an element isolation portion partitioning a device region at the first main surface. The element isolation portion includes a first isolation trench formed at the first main surface; an isolation insulating film at an inner wall of the first isolation trench; and an isolation conductor buried in the first isolation trench via the isolation insulating film. The isolation conductor includes a first isolation conductor formed at a central portion of the first isolation trench; and a second isolation conductor formed at a side of the first isolation conductor with an inner insulating film interposed therebetween. The second isolation conductor includes an inner wall in contact with the inner insulating film and an outer wall, wherein a top of the second isolation conductor includes an inclined wall inclined downward from the outer wall toward the inner wall.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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