DETAILED ACTION
This final Office action is responsive to Applicant’s reply filed June 10, 2026. No claims have been amended. Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed June 10, 2026 have been fully considered but they are not persuasive.
Applicant argues that “the first specific time and the second specific time disclosed in the present invention serve as monitoring thresholds for various stages of the computer system's boot process, rather than a waiting time for a system reset button. Specifically, the system utilizes a timer to verify whether a confirmation signal is received within these predefined specific times at each respective boot stage. If a timeout occurs, the system proactively triggers the output of debug messages to identify the specific point of failure. Therefore, Chiu fails to disclose or teach the aforementioned features. Independent claims 1 and 6 are novel over Chiu.” (Page 3 of Applicant’s response) Similar arguments are relied upon for the dependent claims as well (pages 3-4 of Applicant’s response).
The Examiner respectfully disagrees. There are various possible modes, each of which corresponds to a voltage level of the GPIO pin. For example, an update mode may be assigned a low or high voltage level while a non-update mode might have the opposite voltage level. Each mode has a corresponding power switching waiting time. This is explained in at least paragraphs 20-23 of Chiu:
[0020] In step S230, the control chip 130 determines the power switching waiting time of the power switching unit according to the voltage level of the GPIO pin. In the embodiment, the embedded controller 120 may change the voltage level of the GPIO pin according to the first handshake command, such that the control chip 130 may accordingly adjust the power switching waiting time of the power switching unit according to the change of the voltage level of the GPIO pin.
[0021] In the embodiment, when executing the update mode, the embedded controller 120 may enable the GPIO pin to have a first voltage level (such as a high voltage level or a low voltage level), such that the control chip 130 may set the power switching waiting time to a first time length according to the first voltage level received from the GPIO pin of the embedded controller 120. When the update mode is not executed or execution of the update mode is finished (completed), the embedded controller 120 may enable the GPIO pin to have a second voltage level (such as a low voltage level or a high voltage level), such that the control chip 130 may set the power switching waiting time to a second time length according to the second voltage level received from the GPIO pin of the embedded controller 120. In the embodiment, the first time length is greater than the second time length.
[0022] In the embodiment, when execution of the update mode is finished, the BIOS 110 may output a third handshake command to the embedded controller 120 to notify the embedded controller 120 to end the handshake procedure (i.e., to notify a result of the end of execution of the update mode). The embedded controller 120 may end the handshake procedure according to the third handshake command, and adjust again to recover the power switching waiting time of the power switching unit. The first handshake command, the second handshake command and the third handshake command have a same encoding structure.
[0023] Therefore, the power switching control method of the embodiment and the electronic device 100 executing the power switching control method may automatically extend the power switching waiting time of the power switching unit under the state of executing the update mode, so as to avoid shutdown of the electronic device 100 before the update is completed due to the accidental touch of the power switching unit by the user, which causes boot failure of the electronic device 100 (i.e. it is unable to normally execute the BIOS or start the operating system) at the next time when the user operates the electronic device 100.
The confirmation stage (i.e., mode) defines which timer to use. If the update operation is completed in a timely manner, then the regular GIOS mode resumes (as seen in ¶ 22 of Chiu (cited above). However, if a completion signal is not received during an update mode (e.g., because a user triggers a power switching unit continuously for more than a predefined threshold), then the equivalent of an error occurs and the electronic device is shut down, thereby stopping operation of the BIOS start-up process (as seen in ¶¶ 36-37 of Chiu).
The nature of a debug message is not explicitly defined in the independent claims. A message indicating that shut down needs to occur is implied to be created when a user triggers the power switching unit for more than the predefined threshold. Since the message is related to shutting down a system, it may be interpreted as a type of debug message, especially since the nature of any corresponding functionality associated with a “debug message” is not defined in the claims. Furthermore, in ¶ 27 of Chiu, the absence of receipt of a handshake command within the timer period is indicative of an abnormal BIOS operation (Chiu: ¶ 27 – “Moreover, the embedded controller 120 may further determine whether the BIOS 110 is abnormal according to the confirmation time. When the embedded controller 120 does not receive the (next) first handshake command within 11 seconds, the embedded controller 120 switches the voltage level of the GPIO pin from the first voltage level to the second voltage level (such as switching from a low voltage level back to a high voltage level or switching from the high voltage level back to the low voltage level).”).
It is also noted that the enabling of an input pin of the GPIO device to be at a low level is set in the instance of one of two possible scenarios occurring (i.e., if the first-stage confirmation signal is not received within the first specific time or the second-stage confirmation signal is not received within the second specific time); therefore, the step of enabling is only performed in the method claim if either of these scenarios occurs (and it is possible that neither scenario occurs, which means that the enabling does not occur within the method claims). In the apparatus claims, only one of the conditions needs to be handled by the system since these options are recited in the alternative.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-8, and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chiu et al. (US 2024/0288919).
[Claim 1] Chiu discloses a method for processing a debug message of a computer system, applicable to a computer system, wherein the computer system comprises a general-purpose input/output (GPIO) device, a firmware control device, a basic input/output system (BIOS), a first timer, and a second timer (fig. 5; ¶ 4 – “The disclosure provides an electronic device including a basic input/output system (BIOS), an embedded controller, and a control chip. The BIOS is configured to generate a first handshake command when executing an update mode. The embedded controller is coupled to the BIOS and includes a general-purpose input-output (GPIO) pin. The embedded controller performs a handshake procedure with the BIOS according to the first handshake command, and determines a voltage level of the GPIO pin according to the first handshake command. The control chip is coupled to the GPIO pin of the embedded controller, and is configured to determine a power switching waiting time of a power switching unit according to the voltage level of the GPIO pin.”; ¶ 27 – “Moreover, the embedded controller 120 may further determine whether the BIOS 110 is abnormal according to the confirmation time. When the embedded controller 120 does not receive the (next) first handshake command within 11 seconds, the embedded controller 120 switches the voltage level of the GPIO pin from the first voltage level to the second voltage level (such as switching from a low voltage level back to a high voltage level or switching from the high voltage level back to the low voltage level).”), and the method comprises the following steps:
enabling the first timer to perform timing when the computer system starts up (¶ 16 – “In the embodiment, when the BIOS 110 executes an update mode, the BIOS 110 may perform a handshake procedure with the embedded controller 120, such that the embedded controller 120 may simultaneously control the control chip 130 to adjust a power switching waiting time of the power switching unit. In the embodiment, the power switching waiting time is applied to the electronic device 100 to perform a shutdown procedure (or system reset) when the power switching unit is continuously pressed by a user for more than the power switching waiting time. The update mode means that the BIOS 110 is performing firmware update, but the disclosure is not limited thereto.” An update mode is an example of a computer system start up since an update is initializing operations of the system.; ¶ 23 – “Therefore, the power switching control method of the embodiment and the electronic device 100 executing the power switching control method may automatically extend the power switching waiting time of the power switching unit under the state of executing the update mode, so as to avoid shutdown of the electronic device 100 before the update is completed due to the accidental touch of the power switching unit by the user, which causes boot failure of the electronic device 100 (i.e. it is unable to normally execute the BIOS or start the operating system) at the next time when the user operates the electronic device 100.”; ¶ 19 – “In step S210, when executing the update mode, the BIOS 110 may generate a first handshake command. In the embodiment, the BIOS 110 may output the first handshake command to the embedded controller 120 to notify the embedded controller 120 to perform a handshake procedure.”; ¶ 20 – “In step S230, the control chip 130 determines the power switching waiting time of the power switching unit according to the voltage level of the GPIO pin. In the embodiment, the embedded controller 120 may change the voltage level of the GPIO pin according to the first handshake command, such that the control chip 130 may accordingly adjust the power switching waiting time of the power switching unit according to the change of the voltage level of the GPIO pin.”; ¶ 30 – “The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time.”);
determining, by using the firmware control device, whether a first-stage confirmation signal is received within a first specific time (fig. 5; ¶ 30 – “Referring to FIG. 5, the control chip 130 in FIG. 1 may be specifically implemented as a circuit architecture of a control chip 530 shown in FIG. 5. In the embodiment, the control chip 530 may include a logic circuit 531 and counting units 532, 533. The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time. The counting unit 533 may provide a signal delay effect of a second delay time. To be specific, when the counting units 532, 533 continuously receive signals of a low voltage level (i.e., corresponding to a bit value “0”), the counting units 532, 533 may respectively perform counting according to the first delay time and the second delay time, and respectively output a signal of the low voltage level (i.e., corresponding to the bit value “0”) after counting over the first delay time and the second delay time. If the counting units 532, 533 respectively stop receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) before counting over the first delay time and the second delay time, the counting units 532, 533 stop counting, and re-count when receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) next time.”);
stopping, by using the firmware control device, the first timer and enabling the second timer to perform timing if the first-stage confirmation signal is received (¶ 21 – “In the embodiment, when executing the update mode, the embedded controller 120 may enable the GPIO pin to have a first voltage level (such as a high voltage level or a low voltage level), such that the control chip 130 may set the power switching waiting time to a first time length according to the first voltage level received from the GPIO pin of the embedded controller 120. When the update mode is not executed or execution of the update mode is finished (completed), the embedded controller 120 may enable the GPIO pin to have a second voltage level (such as a low voltage level or a high voltage level), such that the control chip 130 may set the power switching waiting time to a second time length according to the second voltage level received from the GPIO pin of the embedded controller 120. In the embodiment, the first time length is greater than the second time length.”);
determining, by using the firmware control device, whether a second-stage confirmation signal is received within a second specific time (fig. 5; ¶ 30 – “Referring to FIG. 5, the control chip 130 in FIG. 1 may be specifically implemented as a circuit architecture of a control chip 530 shown in FIG. 5. In the embodiment, the control chip 530 may include a logic circuit 531 and counting units 532, 533. The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time. The counting unit 533 may provide a signal delay effect of a second delay time. To be specific, when the counting units 532, 533 continuously receive signals of a low voltage level (i.e., corresponding to a bit value “0”), the counting units 532, 533 may respectively perform counting according to the first delay time and the second delay time, and respectively output a signal of the low voltage level (i.e., corresponding to the bit value “0”) after counting over the first delay time and the second delay time. If the counting units 532, 533 respectively stop receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) before counting over the first delay time and the second delay time, the counting units 532, 533 stop counting, and re-count when receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) next time.”);
stopping, by using the firmware control device, the second timer if the second-stage confirmation signal is received (¶ 30 –"Referring to FIG. 5, the control chip 130 in FIG. 1 may be specifically implemented as a circuit architecture of a control chip 530 shown in FIG. 5. In the embodiment, the control chip 530 may include a logic circuit 531 and counting units 532, 533. The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time. The counting unit 533 may provide a signal delay effect of a second delay time. To be specific, when the counting units 532, 533 continuously receive signals of a low voltage level (i.e., corresponding to a bit value “0”), the counting units 532, 533 may respectively perform counting according to the first delay time and the second delay time, and respectively output a signal of the low voltage level (i.e., corresponding to the bit value “0”) after counting over the first delay time and the second delay time. If the counting units 532, 533 respectively stop receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) before counting over the first delay time and the second delay time, the counting units 532, 533 stop counting, and re-count when receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) next time.”);
enabling an input pin of the GPIO device to be at a low level by using the firmware control device if the first-stage confirmation signal is not received within the first specific time or the second-stage confirmation signal is not received within the second specific time (¶ 27 – “In other words, the BIOS 110 may output the first handshake command 410 to the embedded controller 120 every 10 seconds. Moreover, the embedded controller 120 may further determine whether the BIOS 110 is abnormal according to the confirmation time. When the embedded controller 120 does not receive the (next) first handshake command within 11 seconds, the embedded controller 120 switches the voltage level of the GPIO pin from the first voltage level to the second voltage level (such as switching from a low voltage level back to a high voltage level or switching from the high voltage level back to the low voltage level).”); and
enabling the BIOS to output a debug message based on the low level (fig. 5; ¶ 27 – “Moreover, the embedded controller 120 may further determine whether the BIOS 110 is abnormal according to the confirmation time. When the embedded controller 120 does not receive the (next) first handshake command within 11 seconds, the embedded controller 120 switches the voltage level of the GPIO pin from the first voltage level to the second voltage level (such as switching from a low voltage level back to a high voltage level or switching from the high voltage level back to the low voltage level).”; ¶ 36 – “At this time, the logic circuit 531 may output the low voltage level corresponding to the bit value out of “0” to the counting unit 533 according to the look up result of the above table 1. Moreover, after the delay or counting by the counting unit 533, the control signal 501 of the low voltage level corresponding to the bit value out of “0” is output to the power module or the BIOS of the electronic device. In this way, after the user triggers the power switching unit 550 continuously for 14 seconds, the electronic device may be shut down according to the control signal 501 output by the control chip 530.”).
[Claim 2] Chiu discloses controlling the computer system to restart by using the firmware control device if the first timer reaches the first specific time or the second timer reaches the second specific time (¶ 16 – “In the embodiment, when the BIOS 110 executes an update mode, the BIOS 110 may perform a handshake procedure with the embedded controller 120, such that the embedded controller 120 may simultaneously control the control chip 130 to adjust a power switching waiting time of the power switching unit. In the embodiment, the power switching waiting time is applied to the electronic device 100 to perform a shutdown procedure (or system reset) when the power switching unit is continuously pressed by a user for more than the power switching waiting time. The update mode means that the BIOS 110 is performing firmware update, but the disclosure is not limited thereto.”).
[Claim 3] Chiu discloses continuously executing a startup procedure if the first-stage confirmation signal is received within the first specific time or the second-stage confirmation signal is received within the second specific time (¶ 18 – “In the embodiment, when the BIOS 110 executes the update mode, the BIOS 110 may notify the embedded controller 120, such that the embedded controller 120 may control the control chip 130 to extend the power switching waiting time of the power switching unit. In this way, when the BIOS 110 executes the update mode, the accidental shutdown of the electronic device 100 may be effectively avoided, thereby effectively ensuring the electronic device 100 to be able to boot normally in subsequent use, and/or effectively completing firmware or system update.”; ¶¶ 21-23 – Waiting times may be extended to perform updates, as needed.; ¶ 30 – “Referring to FIG. 5, the control chip 130 in FIG. 1 may be specifically implemented as a circuit architecture of a control chip 530 shown in FIG. 5. In the embodiment, the control chip 530 may include a logic circuit 531 and counting units 532, 533. The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time. The counting unit 533 may provide a signal delay effect of a second delay time.”).
[Claim 5] Chiu discloses controlling the debug message to be outputted through the GPIO device or serial-over-LAN (SOL) of the firmware control device (¶ 27 – “In other words, the BIOS 110 may output the first handshake command 410 to the embedded controller 120 every 10 seconds. Moreover, the embedded controller 120 may further determine whether the BIOS 110 is abnormal according to the confirmation time. When the embedded controller 120 does not receive the (next) first handshake command within 11 seconds, the embedded controller 120 switches the voltage level of the GPIO pin from the first voltage level to the second voltage level (such as switching from a low voltage level back to a high voltage level or switching from the high voltage level back to the low voltage level).”; ¶ 36 – “At this time, the logic circuit 531 may output the low voltage level corresponding to the bit value out of “0” to the counting unit 533 according to the look up result of the above table 1. Moreover, after the delay or counting by the counting unit 533, the control signal 501 of the low voltage level corresponding to the bit value out of “0” is output to the power module or the BIOS of the electronic device. In this way, after the user triggers the power switching unit 550 continuously for 14 seconds, the electronic device may be shut down according to the control signal 501 output by the control chip 530.”).
[Claim 6] Chiu discloses a computer system, comprising:
a GPIO device, comprising an input pin and an output pin (¶ 4 – “The disclosure provides an electronic device including a basic input/output system (BIOS), an embedded controller, and a control chip. The BIOS is configured to generate a first handshake command when executing an update mode. The embedded controller is coupled to the BIOS and includes a general-purpose input-output (GPIO) pin.“);
a firmware control device, electrically connected to the output pin of the GPIO device (¶ 4 – “The disclosure provides an electronic device including a basic input/output system (BIOS), an embedded controller, and a control chip. The BIOS is configured to generate a first handshake command when executing an update mode. The embedded controller is coupled to the BIOS and includes a general-purpose input-output (GPIO) pin.”);
a BIOS, electrically connected to the input pin of the GPIO device (¶ 4 – “The disclosure provides an electronic device including a basic input/output system (BIOS), an embedded controller, and a control chip. The BIOS is configured to generate a first handshake command when executing an update mode. The embedded controller is coupled to the BIOS and includes a general-purpose input-output (GPIO) pin.”) and configured to output a debug message (¶ 27 – “In other words, the BIOS 110 may output the first handshake command 410 to the embedded controller 120 every 10 seconds. Moreover, the embedded controller 120 may further determine whether the BIOS 110 is abnormal according to the confirmation time. When the embedded controller 120 does not receive the (next) first handshake command within 11 seconds, the embedded controller 120 switches the voltage level of the GPIO pin from the first voltage level to the second voltage level (such as switching from a low voltage level back to a high voltage level or switching from the high voltage level back to the low voltage level).”; ¶ 36 – “At this time, the logic circuit 531 may output the low voltage level corresponding to the bit value out of “0” to the counting unit 533 according to the look up result of the above table 1. Moreover, after the delay or counting by the counting unit 533, the control signal 501 of the low voltage level corresponding to the bit value out of “0” is output to the power module or the BIOS of the electronic device. In this way, after the user triggers the power switching unit 550 continuously for 14 seconds, the electronic device may be shut down according to the control signal 501 output by the control chip 530.”);
a first timer, electrically connected to the firmware control device and configured to set a first specific time (fig. 5; ¶ 30 – “Referring to FIG. 5, the control chip 130 in FIG. 1 may be specifically implemented as a circuit architecture of a control chip 530 shown in FIG. 5. In the embodiment, the control chip 530 may include a logic circuit 531 and counting units 532, 533. The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time. The counting unit 533 may provide a signal delay effect of a second delay time. To be specific, when the counting units 532, 533 continuously receive signals of a low voltage level (i.e., corresponding to a bit value “0”), the counting units 532, 533 may respectively perform counting according to the first delay time and the second delay time, and respectively output a signal of the low voltage level (i.e., corresponding to the bit value “0”) after counting over the first delay time and the second delay time. If the counting units 532, 533 respectively stop receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) before counting over the first delay time and the second delay time, the counting units 532, 533 stop counting, and re-count when receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) next time.”; ¶ 23 – “Therefore, the power switching control method of the embodiment and the electronic device 100 executing the power switching control method may automatically extend the power switching waiting time of the power switching unit under the state of executing the update mode, so as to avoid shutdown of the electronic device 100 before the update is completed due to the accidental touch of the power switching unit by the user, which causes boot failure of the electronic device 100 (i.e. it is unable to normally execute the BIOS or start the operating system) at the next time when the user operates the electronic device 100.”; ¶ 19 – “In step S210, when executing the update mode, the BIOS 110 may generate a first handshake command. In the embodiment, the BIOS 110 may output the first handshake command to the embedded controller 120 to notify the embedded controller 120 to perform a handshake procedure.”; ¶ 20 – “In step S230, the control chip 130 determines the power switching waiting time of the power switching unit according to the voltage level of the GPIO pin. In the embodiment, the embedded controller 120 may change the voltage level of the GPIO pin according to the first handshake command, such that the control chip 130 may accordingly adjust the power switching waiting time of the power switching unit according to the change of the voltage level of the GPIO pin.”; ¶ 30 – “The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time.”); and
a second timer, electrically connected to the firmware control device and configured to set a second specific time, wherein when the computer system starts up, the first timer performs timing (¶ 16 – “In the embodiment, when the BIOS 110 executes an update mode, the BIOS 110 may perform a handshake procedure with the embedded controller 120, such that the embedded controller 120 may simultaneously control the control chip 130 to adjust a power switching waiting time of the power switching unit. In the embodiment, the power switching waiting time is applied to the electronic device 100 to perform a shutdown procedure (or system reset) when the power switching unit is continuously pressed by a user for more than the power switching waiting time. The update mode means that the BIOS 110 is performing firmware update, but the disclosure is not limited thereto.” An update mode is an example of a computer system start up since an update is initializing operations of the system.; fig. 5; ¶ 30 – “Referring to FIG. 5, the control chip 130 in FIG. 1 may be specifically implemented as a circuit architecture of a control chip 530 shown in FIG. 5. In the embodiment, the control chip 530 may include a logic circuit 531 and counting units 532, 533. The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time. The counting unit 533 may provide a signal delay effect of a second delay time. To be specific, when the counting units 532, 533 continuously receive signals of a low voltage level (i.e., corresponding to a bit value “0”), the counting units 532, 533 may respectively perform counting according to the first delay time and the second delay time, and respectively output a signal of the low voltage level (i.e., corresponding to the bit value “0”) after counting over the first delay time and the second delay time. If the counting units 532, 533 respectively stop receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) before counting over the first delay time and the second delay time, the counting units 532, 533 stop counting, and re-count when receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) next time.”; ¶ 23 – “Therefore, the power switching control method of the embodiment and the electronic device 100 executing the power switching control method may automatically extend the power switching waiting time of the power switching unit under the state of executing the update mode, so as to avoid shutdown of the electronic device 100 before the update is completed due to the accidental touch of the power switching unit by the user, which causes boot failure of the electronic device 100 (i.e. it is unable to normally execute the BIOS or start the operating system) at the next time when the user operates the electronic device 100.”; ¶ 19 – “In step S210, when executing the update mode, the BIOS 110 may generate a first handshake command. In the embodiment, the BIOS 110 may output the first handshake command to the embedded controller 120 to notify the embedded controller 120 to perform a handshake procedure.”; ¶ 20 – “In step S230, the control chip 130 determines the power switching waiting time of the power switching unit according to the voltage level of the GPIO pin. In the embodiment, the embedded controller 120 may change the voltage level of the GPIO pin according to the first handshake command, such that the control chip 130 may accordingly adjust the power switching waiting time of the power switching unit according to the change of the voltage level of the GPIO pin.”; ¶ 30 – “The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time.”);
if the firmware control device detects that a first-stage confirmation signal is received within the first specific time, the first timer is stopped and the second timer performs timing (¶ 21 – “In the embodiment, when executing the update mode, the embedded controller 120 may enable the GPIO pin to have a first voltage level (such as a high voltage level or a low voltage level), such that the control chip 130 may set the power switching waiting time to a first time length according to the first voltage level received from the GPIO pin of the embedded controller 120. When the update mode is not executed or execution of the update mode is finished (completed), the embedded controller 120 may enable the GPIO pin to have a second voltage level (such as a low voltage level or a high voltage level), such that the control chip 130 may set the power switching waiting time to a second time length according to the second voltage level received from the GPIO pin of the embedded controller 120. In the embodiment, the first time length is greater than the second time length.”);
if the firmware control device detects that the first timer reaches the first specific time, the input pin of the GPIO device is controlled to be at a low level (fig. 5; ¶ 30 – “Referring to FIG. 5, the control chip 130 in FIG. 1 may be specifically implemented as a circuit architecture of a control chip 530 shown in FIG. 5. In the embodiment, the control chip 530 may include a logic circuit 531 and counting units 532, 533. The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time. The counting unit 533 may provide a signal delay effect of a second delay time. To be specific, when the counting units 532, 533 continuously receive signals of a low voltage level (i.e., corresponding to a bit value “0”), the counting units 532, 533 may respectively perform counting according to the first delay time and the second delay time, and respectively output a signal of the low voltage level (i.e., corresponding to the bit value “0”) after counting over the first delay time and the second delay time. If the counting units 532, 533 respectively stop receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) before counting over the first delay time and the second delay time, the counting units 532, 533 stop counting, and re-count when receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) next time.”);
if a second-stage confirmation signal is received within the second specific time, the firmware control device stops the second timer (¶ 30 – “Referring to FIG. 5, the control chip 130 in FIG. 1 may be specifically implemented as a circuit architecture of a control chip 530 shown in FIG. 5. In the embodiment, the control chip 530 may include a logic circuit 531 and counting units 532, 533. The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time. The counting unit 533 may provide a signal delay effect of a second delay time. To be specific, when the counting units 532, 533 continuously receive signals of a low voltage level (i.e., corresponding to a bit value “0”), the counting units 532, 533 may respectively perform counting according to the first delay time and the second delay time, and respectively output a signal of the low voltage level (i.e., corresponding to the bit value “0”) after counting over the first delay time and the second delay time. If the counting units 532, 533 respectively stop receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) before counting over the first delay time and the second delay time, the counting units 532, 533 stop counting, and re-count when receiving the signal of the low voltage level (i.e., corresponding to the bit value “0”) next time.”); and
if the firmware control device detects that the second timer reaches the second specific time, the input pin of the GPIO device is controlled to be at the low level, and the BIOS outputs the debug message in response to the input pin being at the low level (fig. 5; ¶ 27 – “Moreover, the embedded controller 120 may further determine whether the BIOS 110 is abnormal according to the confirmation time. When the embedded controller 120 does not receive the (next) first handshake command within 11 seconds, the embedded controller 120 switches the voltage level of the GPIO pin from the first voltage level to the second voltage level (such as switching from a low voltage level back to a high voltage level or switching from the high voltage level back to the low voltage level).”; ¶ 36 – “At this time, the logic circuit 531 may output the low voltage level corresponding to the bit value out of “0” to the counting unit 533 according to the look up result of the above table 1. Moreover, after the delay or counting by the counting unit 533, the control signal 501 of the low voltage level corresponding to the bit value out of “0” is output to the power module or the BIOS of the electronic device. In this way, after the user triggers the power switching unit 550 continuously for 14 seconds, the electronic device may be shut down according to the control signal 501 output by the control chip 530.”).
[Claim 7] Chiu discloses wherein the firmware control device controls the computer system to restart if the first timer reaches the first specific time or the second timer reaches the second specific time (¶ 16 – “In the embodiment, when the BIOS 110 executes an update mode, the BIOS 110 may perform a handshake procedure with the embedded controller 120, such that the embedded controller 120 may simultaneously control the control chip 130 to adjust a power switching waiting time of the power switching unit. In the embodiment, the power switching waiting time is applied to the electronic device 100 to perform a shutdown procedure (or system reset) when the power switching unit is continuously pressed by a user for more than the power switching waiting time. The update mode means that the BIOS 110 is performing firmware update, but the disclosure is not limited thereto.”).
[Claim 8] Chiu discloses wherein a startup procedure is continuously executed if the firmware control device receives the first-stage confirmation signal within the first specific time or receives the second-stage confirmation signal within the second specific time (¶ 18 – “In the embodiment, when the BIOS 110 executes the update mode, the BIOS 110 may notify the embedded controller 120, such that the embedded controller 120 may control the control chip 130 to extend the power switching waiting time of the power switching unit. In this way, when the BIOS 110 executes the update mode, the accidental shutdown of the electronic device 100 may be effectively avoided, thereby effectively ensuring the electronic device 100 to be able to boot normally in subsequent use, and/or effectively completing firmware or system update.”; ¶¶ 21-23 – Waiting times may be extended to perform updates, as needed.; ¶ 30 – “Referring to FIG. 5, the control chip 130 in FIG. 1 may be specifically implemented as a circuit architecture of a control chip 530 shown in FIG. 5. In the embodiment, the control chip 530 may include a logic circuit 531 and counting units 532, 533. The counting units 532, 533 may be, for example, composed of counters and/or delay generators. The counting unit 532 may provide a signal delay effect of a first delay time. The counting unit 533 may provide a signal delay effect of a second delay time.”).
[Claim 10] Chiu discloses wherein the debug message is outputted through the GPIO device or SOL of the firmware control device (¶ 27 – “In other words, the BIOS 110 may output the first handshake command 410 to the embedded controller 120 every 10 seconds. Moreover, the embedded controller 120 may further determine whether the BIOS 110 is abnormal according to the confirmation time. When the embedded controller 120 does not receive the (next) first handshake command within 11 seconds, the embedded controller 120 switches the voltage level of the GPIO pin from the first voltage level to the second voltage level (such as switching from a low voltage level back to a high voltage level or switching from the high voltage level back to the low voltage level).”; ¶ 36 – “At this time, the logic circuit 531 may output the low voltage level corresponding to the bit value out of “0” to the counting unit 533 according to the look up result of the above table 1. Moreover, after the delay or counting by the counting unit 533, the control signal 501 of the low voltage level corresponding to the bit value out of “0” is output to the power module or the BIOS of the electronic device. In this way, after the user triggers the power switching unit 550 continuously for 14 seconds, the electronic device may be shut down according to the control signal 501 output by the control chip 530.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 2024/0288919), as applied to claim 1 (for claim 4) and to claim 6 (for claims 9 and 11) above, in view of Balakrishnan et al. (US 2018/0081550).
[Claims 4, 9, 11] Chiu uses an embedded control and a control chip (Chiu: ¶ 15). Chiu does not explicitly disclose:
[Claim 4] controlling the input pin of the GPIO device to be at the low level by executing an intelligent platform management interface (IPMI) command;
[Claim 9] wherein the input pin of the GPIO device is further controlled to be at the low level by executing an IPMI command.
[Claim 11] wherein the firmware control device is a baseboard management controller (BMC), a system input/output chip (SIO), a complex programmable logic device (CPLD), or a field programmable gate array (FPGA).
Balakrishnan explains, “The term “baseboard management controller” or its abbreviation “BMC” is the intelligence in the IPMI architecture. It is a specialized microcontroller embedded on the motherboard of a computer, which manages the interface between the system management software and the platform hardware.” (Balakrishnan: ¶ 46) The BMC may be a management controller that includes a GPIO (Balakrishnan: ¶ 64 – “FIG. 2 schematically depicts a configuration for synchronizing the management controller with the RAID according to certain embodiments of the present disclosure. In the embodiments, a control circuit 120 is provided to communicate the host computing device 130 with the management controller 110. In certain embodiments, the control circuit 120 is a complex programmable logic device (CPLD). In certain embodiments, the management controller 110 is a BMC. As shown in FIG. 2, the management controller 110 includes a processor 112, a general-purpose input/output (GPIO) 113, a memory 114, and a non-volatile memory 116.”). The GPIO is a generic pin electrically connected to the control circuit and its voltage may be controlled, including to be set at low voltage (Balakrishnan: ¶ 66).
Additionally, Balakrishnan discloses wherein the firmware control device is a baseboard management controller (BMC) (Balakrishnan: ¶ 6), a system input/output chip (SIO), a complex programmable logic device (CPLD) (Balakrishnan: ¶ 7), or a field programmable gate array (FPGA) (Balakrishnan: ¶¶ 42, 50).
Given that Chiu manages GPIO devices and discusses the ability to set a pin of the GPIO device to be at a low voltage (as discussed in regard to the independent claims above), the Examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of Applicant’s invention to modify Chiu to perform the step of:
[Claim 4] controlling the input pin of the GPIO device to be at the low level by executing an intelligent platform management interface (IPMI) command;
[Claim 9] wherein the input pin of the GPIO device is further controlled to be at the low level by executing an IPMI command; and
[Claim 11] wherein the firmware control device is a baseboard management controller (BMC), a system input/output chip (SIO), a complex programmable logic device (CPLD), or a field programmable gate array (FPGA)
since the substitution of Chiu’s controllers (such as the embedded control and control chip) for any of Balakrishnan’s controllers (including a BMC, CPLD, or an FPGA), including the controller (such as a BMC) that executes intelligent platform management interface (IPMI) commands (e.g., to control the input pin of the GPIO device to be at the low level) would have been well within the technical capability of those skilled in the art prior to Applicant’s invention and such a substitution would have yielded predictable and expected results.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 2024/0288919), as applied to claim 6 above, in view of Lam (US 2003/0005275).
[Claim 12] Chiu’s timers facilitate a startup event and a potential reset event (Chiu: ¶ 16 – “In the embodiment, when the BIOS 110 executes an update mode, the BIOS 110 may perform a handshake procedure with the embedded controller 120, such that the embedded controller 120 may simultaneously control the control chip 130 to adjust a power switching waiting time of the power switching unit. In the embodiment, the power switching waiting time is applied to the electronic device 100 to perform a shutdown procedure (or system reset) when the power switching unit is continuously pressed by a user for more than the power switching waiting time. The update mode means that the BIOS 110 is performing firmware update, but the disclosure is not limited thereto.” An update mode is an example of a computer system start up since an update is initializing operations of the system.). Chiu does not explicitly disclose wherein the first timer is a fault resilient boot 3 (FRB-3) device, and the second timer is a fault resilient boot 2 (FRB-2) device.
Lam discloses wherein the first timer is a fault resilient boot 3 (FRB-3) device, and the second timer is a fault resilient boot 2 (FRB-2) device (Lam: ¶ 13 – “The next level of the fault resilient booting, FRB-2, involves the use of the watchdog timer to backup the operation of the baseboard management controller during the power-on self test. BIOS sets a bit in the baseboard management controller to indicate that BIOS is in the FRB-2 phase. This bit is set after it is determined which processor is the bootstrap processor. BIOS then sets the FRB-2 bit, loads the watchdog timer with a new time-out interval and disables FRB-3. Using this process, there is no gap in the watchdog timer coverage between FRB-3 and FRB-2. If the FRB-2 phase is successful, BIOS disables the FRB-2 time-out prior to exiting the power on self test. The baseboard management controller provides commands for this purpose. This is generally done prior to initiating the option ROM scan.”).
Given that Chiu performs timing operations corresponding to Lam’s FRB-3 and FRB-2, the Examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of Applicant’s invention to modify Chiu wherein the first timer is a fault resilient boot 3 (FRB-3) device, and the second timer is a fault resilient boot 2 (FRB-2) device since the substitution of Chiu’s timing devices for Lam’s FRB-3 and FRB-2 devices would have been well within the technical capability of those skilled in the art prior to Applicant’s invention and such a substitution would have yielded predictable and expected results.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUSANNA M DIAZ whose telephone number is (571)272-6733. The examiner can normally be reached M-F, 8 am-4:30 pm.
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/SUSANNA M. DIAZ/
Primary Examiner
Art Unit 3625A
Prosecution Insights