DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed May 2, 2024.
Claims 1-4, 6-7, 9-10, 15-16, 22-25, 40, 43-46 and 61 are pending. Claims 5, 8, 11-14, 17-21, 26-39, 41-42, 47-60 and 62-63 are canceled. Claims 1, 22 and 43 are independent.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 22, 40, 43 and 61 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. 2019/0371418) in view of Parthasarathy et al. (U.S. 2022/0076757; hereinafter “Parthasarathy”).
Regarding independent claim 1, Kim teaches a method (see page 1, par. 0002), comprising:
performing an iterative programming operation to program a non-volatile memory device having at least a plurality of memory cells, where the plurality of memory cells are connected through a word line (see page 1, par. 0006), the iterative programming operation having a sequence of at least 1 to n-th programming stages, n being a positive integer that is greater than 1 (“program operations are repeated,” see page 5, par. 0072-0073), the n-th programming stage includes,
applying an n-th program voltage to the word line connected to the plurality of memory cells (see page 4, par. 0060), and
performing a verification operation associated with a particular verification voltage on the plurality of memory cells to generate an n-th verification result value (see page 6, par. 0084), the n-th verification result value indicating a number of memory cells of the plurality of memory cells having a threshold voltage that is equal to or greater than the particular verification voltage at the n-th programming stage (see page 6, par. 0085); and
performing at least an n-th model stage of an iterative model that utilizes the n-th verification result value to determine an n-th probability value indicating a probability associated with occurrence of at least one programming anomaly in the 1 to n-th programming stages of the iterative programming operation (“determine the possibility that a program operation for a selected word line may cause an error,” see page 6, par. 0085, see also page 7, par. 0100).
However, Kim is silent with respect to utilizes the n-th verification result value and n-th historical data associated with at least an (n-1)-th programming stage of the iterative programming operation to determine an n-th probability value indicating a probability associated with occurrence of at least one programing anomaly.
Parthasarathy teaches the step of performing at least an n-th model stage of an iterative model that utilizes the n-th verification result value (“count of all cells with threshold voltages greater than the applied read voltage,” see page 2, par. 0019) and n-th historical data associated with at least an (n-1)-th programming stage of the iterative programming operation (“historical data patterns,” see page 8, par. 0108) to determine an n-th probability value indicating a probability associated with occurrence of at least one programing anomaly (“detecting anomaly,” see page 8, par. 0108).
Since Parthasarathy and Kim are from the same field of endeavor, the teachings described by Parthasarathy would have been recognized in the pertinent art of Kim.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine teachings of Parthasarathy with the teachings of Kim for the purpose of mitigate reliability concerns, see Parthasarathy’s page 2, par. 0018.
Regarding independent claim 22, Kim teaches a storage device (Fig. 1), comprising:
a non-volatile memory device (Fig. 6: 150) having at least a plurality of memory cells (Fig. 6: 330), where the plurality of memory cells are connected through a word line (Fig. 6: WL); and
a processor (Fig. 6: 610) configured to
perform an iterative programming operation to program the non-volatile memory device, the iterative programming operation having a sequence of at least 1 to n-th programming stages, n being a positive integer that is greater than 1 (“program operations are repeated,” see page 5, par. 0072-0073), the n-th programming stage includes,
applying an n-th program voltage to the word line connected to the plurality of memory cells (see page 4, par. 0060), and
performing a verification operation associated with a particular verification voltage on the plurality of memory cells to generate an n-th verification result value (see page 6, par. 0084), the n-th verification result value indicating a number of memory cells of the plurality of memory cells having a threshold voltage that is equal to or greater than the particular verification voltage at the n-th programming stage (see page 6, par. 0085), and
perform at least an n-th model stage of an iterative model that utilizes the n-th verification result value to determine an n-th probability value indicating a probability associated with occurrence of at least one programming anomaly in the 1 to n-th programming stages of the iterative programming operation (“determine the possibility that a program operation for a selected word line may cause an error,” see page 6, par. 0085, see also page 7, par. 0100).
However, Kim is silent with respect to utilizes the n-th verification result value and n-th historical data associated with at least an (n-1)-th programming stage of the iterative programming operation to determine an n-th probability value indicating a probability associated with occurrence of at least one programing anomaly.
Parthasarathy teaches the step of performing at least an n-th model stage of an iterative model that utilizes the n-th verification result value (“count of all cells with threshold voltages greater than the applied read voltage,” see page 2, par. 0019) and n-th historical data associated with at least an (n-1)-th programming stage of the iterative programming operation (“historical data patterns,” see page 8, par. 0108) to determine an n-th probability value indicating a probability associated with occurrence of at least one programing anomaly (“detecting anomaly,” see page 8, par. 0108).
Since Parthasarathy and Kim are from the same field of endeavor, the teachings described by Parthasarathy would have been recognized in the pertinent art of Kim.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine teachings of Parthasarathy with the teachings of Kim for the purpose of mitigate reliability concerns, see Parthasarathy’s page 2, par. 0018.
Regarding claim 40, Kim in combination with Parthasarathy teaches the limitations with respect to claim 22.
Furthermore, Kim teaches an electronic device (Fig. 6: 310, 320, 610, 630 and 650), comprising a control circuit configured to communicate with the storage device to cause data to be written to the storage device and/or to be read from the storage device (Fig. 6: 320).
Regarding independent claim 43, Kim teaches a non-transitory computer-readable storage medium having a computer program recorded thereon, the computer program (see page , par. 0064), when executed by at least one processor (Fig. 6: 610), is configured to cause the at least one processor to perform a method, the method comprising:
performing an iterative programming operation to program a non-volatile memory device having at least a plurality of memory cells, where the plurality of memory cells are connected through a word line (see page 1, par. 0006), the iterative programming operation having a sequence of at least 1 to n-th programming stages, n being a positive integer that is greater than 1 (“program operations are repeated,” see page 5, par. 0072-0073), the n-th programming stage includes,
applying an n-th program voltage to the word line connected to the plurality of memory cells (see page 4, par. 0060), and
performing a verification operation associated with a particular verification voltage on the plurality of memory cells to generate an n-th verification result value (see page 6, par. 0084), the n-th verification result value indicating a number of memory cells of the plurality of memory cells having a threshold voltage that is equal to or greater than the particular verification voltage at the n-th programming stage (see page 6, par. 0085); and
performing at least an n-th model stage of an iterative model that utilizes the n-th verification result value to determine an n-th probability value indicating a probability associated with occurrence of at least one programming anomaly in the 1 to n-th programming stages of the iterative programming operation (“determine the possibility that a program operation for a selected word line may cause an error,” see page 6, par. 0085, see also page 7, par. 0100).
However, Kim is silent with respect to utilizes the n-th verification result value and n-th historical data associated with at least an (n-1)-th programming stage of the iterative programming operation to determine an n-th probability value indicating a probability associated with occurrence of at least one programing anomaly.
Parthasarathy teaches the step of performing at least an n-th model stage of an iterative model that utilizes the n-th verification result value (“count of all cells with threshold voltages greater than the applied read voltage,” see page 2, par. 0019) and n-th historical data associated with at least an (n-1)-th programming stage of the iterative programming operation (“historical data patterns,” see page 8, par. 0108) to determine an n-th probability value indicating a probability associated with occurrence of at least one programing anomaly (“detecting anomaly,” see page 8, par. 0108).
Since Parthasarathy and Kim are from the same field of endeavor, the teachings described by Parthasarathy would have been recognized in the pertinent art of Kim.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine teachings of Parthasarathy with the teachings of Kim for the purpose of mitigate reliability concerns, see Parthasarathy’s page 2, par. 0018.
Regarding claim 61, Kim in combination with Parthasarathy teaches the limitations with respect to claim 43.
Furthermore, Kim teaches an electronic device (Fig. 6: 310, 320, 610, 630 and 650), comprising a processor (Fig. 6: 610) configured to execute the computer program recorded on the non-transitory computer-readable storage medium to perform the method (Fig. 6: 320).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Parthasarathy as applied to claim 1 above, and further in view of He (U.S. 2023/0230644).
Regarding claim 6, Kim in combination with Parthasarathy teaches the limitations with respect to claim 1.
However, the combination is silent with respect to determining that the at least one programming anomaly has occurred in the 1 to n-th programming stages of the iterative programming operation based on determining that the n-th probability value at least meets an n-th threshold probability value.
He teaches the step of determining that the at least one programming anomaly has occurred in the 1 to n-th programming stages of the iterative programming operation based on determining that the n-th probability value at least meets an n-th threshold probability value (see page 13, par. 0155-0157).
Since He, Parthasarathy and Kim are from the same field of endeavor, the teachings described by He would have been recognized in the pertinent art of Kim in combination with Parthasarathy.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine teachings of He with the teachings of Kim in combination with Parthasarathy for the purpose of provides a system that can provide data protection for memory, see He’s page 2, par. 0018.
Allowable Subject Matter
Claims 2-4, 7, 9-10, 15-16, 23-25 and 44-46 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, there is no teaching or suggestion in the prior art of record to provide the recited steps of performing a plurality of verification operations on the plurality of memory cells to generate a plurality of n-th verification result values, wherein the plurality of verification operations include the verification operation, the plurality of verification operations are associated with separate, respective verification voltages of a plurality of verification voltages that are different from each other, the plurality of n-th verification result values include the n-th verification result value, and each separate n-th verification result value of the plurality of n-th verification result values indicates a separate number of memory cells of the plurality of memory cells having a threshold voltage that is equal to or greater than a separate verification voltage of the plurality of verification voltages at the n-th programming stage; and performing an n-th model stage of one or more iterative models that utilize the plurality of n-th verification result values and historical data associated with at least the (n-1)-th programming stage of the iterative programming operation to determine a plurality of n-th probability values, wherein the plurality of n-th probability values include the n-th probability value, each separate n-th probability value is determined based on applying a separate n-th verification result of the plurality of n-th verification result values to the one or more iterative models, and each separate n-th probability value of the plurality of n-th probability values indicates a separate probability associated with occurrence of at least one programming anomaly in the 1 to n-th programming stages of the iterative programming operation.
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited causing a recovery action to be performed in response to determining that the at least one programming anomaly has occurred in the 1 to n-th programming stages of the iterative programming operation, the recovery action including at least one of an error correction operation, terminating the iterative programming operation prior to completion of a final programming stage of the iterative programming operation, or transmitting a warning signal to provide an indication of the occurrence of the at least one programming anomaly.
With respect to claim 9, there is no teaching or suggestion in the prior art of record to provide the recited step of wherein the n-th model stage of the iterative model is performed at least partially concurrently with performing an (n+1)-th programming stage of the iterative programming operation at an (n+1)-th time step.
With respect to claim 10, there is no teaching or suggestion in the prior art of record to provide the recited step of determining the n-th probability value includes determining an n-th conditional probability distribution based on performing at least the n-th model stage of the iterative model, the n-th conditional probability distribution indicating a distribution of probability values corresponding to verification result values, and determining a probability value indicated by the n-th conditional probability distribution that corresponds to the n-th verification result value as the n-th probability value.
With respect to claim 15, there is no teaching or suggestion in the prior art of record to provide the recited iterative programming operation includes N total stages, n being less than N, and the method further includes determining that the at least one programming anomaly has occurred in the 1 to n-th programming stages of the iterative programming operation prior to completion of an N-th programming stage of the iterative programming operation.
With respect to claim 23, there is no teaching or suggestion in the prior art of record to provide the recited processor further configured to execute the program of instructions to perform a plurality of verification operations on the plurality of memory cells to generate a plurality of n-th verification result values, wherein the plurality of verification operations include the verification operation, the plurality of verification operations are associated with separate, respective verification voltages of a plurality of verification voltages that are different from each other, the plurality of n-th verification result values include the n-the verification result value, and each separate n-th verification result value of the plurality of n-th verification result values indicates a separate number of memory cells of the plurality of memory cells having a threshold voltage that is equal to or greater than a separate verification voltage of the plurality of verification voltages at the n-th programming stage, and perform an n-th model stage of one or more iterative models that utilize the plurality of n-th verification result values and historical data associated with at least the (n-1)-th programming stage of the iterative programming operation to determine a plurality of n-th probability values, wherein the plurality of n-th probability values include the n-th probability value, each separate n-th probability value is determined based on applying a separate n-th verification result of the plurality of n-th verification result values to the one or more iterative models, and each separate n-th probability value of the plurality of n-th probability values indicates a separate probability associated with occurrence of at least one programming anomaly in the 1 to n-th programming stages of the iterative programming operation.
With respect to claim 44, there is no teaching or suggestion in the prior art of record to provide the recited performing a plurality of verification operations on the plurality of memory cells to generate a plurality of n-th verification result values, wherein the plurality of verification operations include the verification operation, the plurality of verification operations are associated with separate, respective verification voltages of a plurality of verification voltages that are different from each other, the plurality of n-th verification result values include the n-the verification result value, and each separate n-th verification result value of the plurality of n-th verification result values indicates a separate number of memory cells of the plurality of memory cells having a threshold voltage that is equal to or greater than a separate verification voltage of the plurality of verification voltages at the n-th programming stage; and performing an n-th model stage of one or more iterative models that utilize the plurality of n-th verification result values and historical data associated with at least the (n-1)-th programming stage of the iterative programming operation to determine a plurality of n-th probability values, wherein the plurality of n-th probability values include the n-th probability value, each separate n-th probability value is determined based on applying a separate n-th verification result of the plurality of n-th verification result values to the one or more iterative models, and each separate n-th probability value of the plurality of n-th probability values indicates a separate probability associated with occurrence of at least one programming anomaly in the 1 to n-th programming stages of the iterative programming operation.
Conclusion
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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