CTNF 18/653,498 CTNF 81034 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Claims 15-20 are objected to because of the following informalities: In claim 15, line 2, substitute “PIC” with -- photonic integrated circuit (PIC) -- before “wafer.” Claims 16-20 depend from claim 15, so they are objected for the same reason. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-3 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ecton et al. (US Pub. 2024/0178207; hereinafter “Ecton”) . Regarding Claim 1 , Ecton discloses a device, comprising: a glass substrate 103 having a plurality of through-glass vias (TGVs) 110 (page 6, paragraph 72; see fig. 1A), an oxide layer 108 (page 9, paragraph 86; see fig. 1C), and metal contacts 132 (page 9, paragraph 86; see fig. 1C) coupled with the TGVs 110 (see fig. 1A); and a silicon photonic layer 104 (page 6, paragraph 73; page 7, paragraph 74) having metal pads 134 and an oxide layer 108 (page 9, paragraph 86; see fig. 1C), the metal pads 134 are bonded with the metal contacts 132 and the oxide layer 108 of the silicon photonic layer 104 is bonded with the oxide layer 108 of the glass substrate 103 such that the silicon photonic layer 104 is hybrid bonded to the glass substrate 103 by a metal-to-metal, oxide-to-oxide hybrid bond (page 6, paragraph 71; page 9, paragraph 86; see figs. 1A and 1C). Regarding Claim 2 , Ecton discloses wherein the silicon photonic layer 104 has a substrate-interface surface (bottom surface of a layer 102-2 of an interconnect 106) arranged in contact with the glass substrate 103 (top surface of a layer 102-1 of the interconnect 106) (page 9, paragraph 86; see fig. 1C), and wherein at least one of the metal pads 134 is connected to a hub layer 105 (active surface; page 7, paragraph 74) of the silicon photonic layer 104 by a metal via (page 4, paragraph 42; see fig. 1A), the at least one metal pad 134 is arranged flush with the substrate-interface surface (bottom surface of the layer 102-2) (see fig. 1C) and bonded with one of the metal contacts 132 of the glass substrate 103 (page 9, paragraph 86; see figs. 1A and 1C). Regarding Claim 3 , Ecton discloses wherein the silicon photonic layer 104 has a buried insulation layer (an insulation layer between the active surface 105 and metal pads 134; see fig. 1A) and an optical detector 168 (photodetector; page 7, paragraph 75) arranged on one side (top side) of the buried insulation layer (see fig. 1A), and wherein the at least one metal pad 134 that is arranged flush with the substrate-interface surface (bottom surface of the layer 102-2) (see fig. 1C) is arranged on a side (bottom surface) of the buried insulation layer opposite the optical detector 168 (see fig. 1A) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ecton . Regarding Claim 6 , Ecton fails to disclose explicitly wherein a thickness ratio is defined as a thickness of the glass substrate to a thickness of the silicon photonic layer, and wherein the thickness ratio is between 5:1 and 40:1. However, the application does not demonstrate that the claimed ratio is critical or produces any unexpected results. In the absence of evidence of demonstrating criticality, the recited range is considered an obvious optimization of a known parameter and does not patentably distinguish the claimed invention from the prior art. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller , 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson , 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele , 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)). Furthermore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select an appropriate relative thickness of the glass substrate and the silicon photonic layer, including a ratio falling within the claimed range, as such dimensions are recognized as variables that affect characteristics such as mechanical support, structural integrity, manufacturability, and integration of the photonic structure . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4, 5, 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claim 4 recites the silicon photonic layer has a substrate-interface surface and a stackable-interface surface defining a thickness of the silicon photonic layer, and wherein the silicon photonic layer has a stackable metal via arranged flush with the stackable-interface surface. Claim 5 recites an electrical integrated circuit (EIC) bonded to a stackable-interface surface of the silicon photonic layer; a light source bonded to the stackable-interface surface; and an application-specific integrated circuit (ASIC) bonded to the stackable-interface surface, the ASIC being electrically coupled with the EIC by one or more electrical wires extending, at least in part, through the silicon photonic layer. Claim 7 recites the silicon photonic layer has a waveguide embedded therein and the glass substrate has a waveguide embedded therein, and wherein the waveguide of the silicon photonic layer is coupled with the waveguide of the glass substrate by an evanescent optical coupling. Claim 8 recites the silicon photonic layer has a waveguide embedded therein, and the glass substrate has one or more waveguides and a passive optical device embedded therein, and wherein the waveguide of the silicon photonic layer is coupled with the one or more waveguides of the glass substrate by an evanescent optical coupling. These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record. Claims 9-14 are allowed, and claims 15-20 will be allowed upon correcting the objection set forth above. The following is an examiner’s statement of reasons for allowance: Claim 9 recites an electronic integrated circuit (EIC) stacked on the silicon photonic layer and coupled with the plurality of stackable metal vias. Claim 15 recites removing the wafer-level silicon handle of the PIC wafer while the wafer-level silicon photonic layer remains hybrid bonded to the glass substrate wafer; attaching a plurality of integrated circuits to the wafer-level silicon photonic layer; wherein in performing the wafer singulation, at least one electro-optical package of the electro-optical packages is diced so that an optical interface of the silicon photonic layer is created by the dicing. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record. Claims 10-14 and 16-20 variously depend from claim 9 or 15, so they are allowed or will be allowed for the same reason . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHEUNG LEE/Primary Examiner, Art Unit 2812 June 11, 2026 Application/Control Number: 18/653,498 Page 2 Art Unit: 2812 Application/Control Number: 18/653,498 Page 4 Art Unit: 2812 Application/Control Number: 18/653,498 Page 5 Art Unit: 2812 Application/Control Number: 18/653,498 Page 6 Art Unit: 2812 Application/Control Number: 18/653,498 Page 7 Art Unit: 2812 Application/Control Number: 18/653,498 Page 8 Art Unit: 2812
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