Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species I (Claims 1-15) in the reply filed on September 9, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-10, and 13-15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bhushan et al. (Pub No. US 20250309121 A1), hereinafter referred to as Bhushan.
Regarding claim 1, Bhushan teaches A semiconductor structure, comprising: a plurality of memory dies in a stacked configuration (Fig. 4F, memory chip 405-a, memory chip 405-b, memory stack 420; ¶73-90); and at least one through-chip via (TCV) that extends through the plurality of memory dies wherein the at least one TCV is adapted to provide power to the plurality of memory dies (Fig. 4G, vias 455; ¶87).
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Regarding claim 2, Bhushan further teaches a substrate (Fig. 5, method 505; ¶92, 97), wherein the at least one TCV is adapted to provide the power from the substrate to a power distribution bus, wherein the power distribution bus is located above the plurality of memory dies and is connected to at least one through-silicon via (TSV) that extends through one of the plurality of memory dies and is adapted to provide the power from the power distribution bus to the plurality of memory dies (Figs. 4F-4G, vias 455, redistribution layers 450, vias 410-a,410-b, memory chip 405-a, memory chip 405-b, memory stack 420; ¶87, 97).
Regarding claim 6, Bhushan further teaches the at least one TCV is adapted to provide signals to the plurality of memory dies (Fig. 4G, vias 455; ¶87).
Regarding claim 7, Bhushan further teaches a plurality of through-silicon vias (TSVs) extending through each of the plurality of memory dies, wherein the plurality of TSVs is adapted to transmit signals between any two memory dies of the plurality of memory dies that are located next to each other (Figs. 4F-4G, vias 410-a,410-b, memory chip 405-a, memory chip 405-b, memory stack 420; ¶73-90).
Regarding claim 8, Bhushan further teaches a logic die located above the plurality of memory dies and electrically joined to the plurality of memory dies (Figs. 4F-4G, logic chip 440, memory chip 405-a, memory chip 405-b, memory stack 420, vias 410-a,410-b,410-c; ¶73-90).
Regarding claim 9, Bhushan further teaches a semiconductor structure, comprising: a plurality of memory dies in a stacked configuration (Fig. 4F, memory chip 405-a, memory chip 405-b, memory stack 420; ¶73-90); a logic die located above the plurality of memory dies (Figs. 4F-4G, logic chip 440; ¶73-90); a plurality of through-chip vias (TCVs) that extend through the plurality of memory dies wherein the plurality of TCVs are adapted to provide power to the logic die (Fig. 4G, vias 455; ¶87); and a plurality of through-silicon vias (TSVs) extending through each of the plurality of memory dies and adapted to transmit power from the logic die to the plurality of memory dies (Figs. 4F-4G, vias 410-a,410-b,410-c; ¶73-90).
Regarding claim 10, Bhushan further teaches a substrate located below the plurality of memory dies, wherein at least one of the plurality of TCVs is adapted to provide the power from the substrate to the logic die (Fig. 4G, vias 455, logic chip 440, memory chip 405-a, memory chip 405-b, memory stack 420; ¶73-90, 92, 97).
Regarding claim 13, Bhushan further teaches a power distribution bus located above the plurality of memory dies and adapted to provide power to the plurality of memory dies (Figs. 4F-4G, vias 455, redistribution layers 450, vias 410-a,410-b, memory chip 405-a, memory chip 405-b, memory stack 420; ¶87, 97).
Regarding claim 14, Bhushan further teaches the plurality of TSVs is adapted to transmit signals between any two memory dies of the plurality of memory dies that are located next to each other (Figs. 4F-4G, vias 410-a,410-b, memory chip 405-a, memory chip 405-b, memory stack 420; ¶73-90).
Regarding claim 15, Bhushan further teaches the logic die is electrically joined to the plurality of memory dies (Figs. 4F-4G, logic chip 440, memory chip 405-a, memory chip 405-b, memory stack 420, vias 410-a,410-b,410-c; ¶73-90).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 5, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bhushan in view of Fujiwara et al. (Pub. No. US 20230170281 A1), hereinafter referred to as Fujiwara.
Regarding claim 3, Bhushan teaches the semiconductor structure of claim 2 and further teaches a logic die (Figs. 4F-4G, logic chip 440; ¶73-90), and the power distribution bus (Figs. 4F-4G, redistribution layers 450; ¶73-90), wherein the at least one TCV is adapted to provide power to the logic die (Fig. 4G, vias 455; ¶87). However, Bhushan does not explicitly teach a logic die located above the power distribution bus.
Fujiwara teaches a logic die located above the power distribution bus (Fig. 4, logic die 400L, power distribution structure 400PDS; ¶47-63).
Bhushan and Fujiwara are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Bhushan with the teachings of Fujiwara such that the logic die is located above the power distribution bus. For the purpose of improving the electrical functionality of the device, as recognized by Fujiwara. Also, for improved thermal characteristics and heat management of the device by having the highest heat generating device, the logic die, being on the top of the stack.
Regarding claim 5, Bhushan teaches the semiconductor structure of claim 1. Bhushan further teaches the at least one TCV is electrically connected to a substrate (¶97). However, Bhushan does not explicitly teach the at least one TCV is adapted to provide a ground connection to a substrate.
Fujiwara teaches a substrate configured to receive and distribute a ground voltage (Fig. 4, substrate 400S, bump structures 400B; ¶52).
Bhushan and Fujiwara are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Bhushan with the teachings of Fujiwara such that the at least one TCV is adapted to provide a ground connection to a substrate. For the purpose of having optimal electrical functionality of the device.
Regarding claim 11, Bhushan teaches the semiconductor structure of claim 10. Bhushan further teaches the at least one TCV is electrically connected to a substrate (¶97). However, Bhushan does not explicitly teach at least one of the plurality of TCVs is adapted to provide a ground connection to a substrate.
Fujiwara teaches a substrate configured to receive and distribute a ground voltage (Fig. 4, substrate 400S, bump structures 400B; ¶52).
Bhushan and Fujiwara are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Bhushan with the teachings of Fujiwara such that at least one of the plurality of TCVs is adapted to provide a ground connection to a substrate. For the purpose of having optimal electrical functionality of the device.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bhushan in view of Fujiwara as applied to claim 3 above, and further in view of Mathuriya et al. (US Patent No. 12,086,410), hereinafter referred to as Mathuriya.
Regarding claim 4, Bhushan in view of Fujiwara does not teach a heat sink located above the logic die and adapted to remove heat from the logic die and the plurality of memory dies.
Mathuriya teaches a heat sink located above the logic die and adapted to remove heat from the logic die and the plurality of memory dies (Fig. 4B, heat sink 315, compute die 402; Col. 13, line 29 - Col. 15, line 64).
Bhushan, Fujiwara, and Mathuriya are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Bhushan in view of Fujiwara with the teachings of Mathuriya such that a heat sink is located above the logic die and adapted to remove heat from the logic die and the plurality of memory dies. For the purpose of improved thermal characteristics and heat management of the device, as recognized by Mathuriya.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bhushan in view of Mathuriya.
Regarding claim 12, Bhushan teaches the semiconductor structure of claim 9. However, Bhushan does not teach a heat sink located above the logic die and adapted to remove heat from the logic die and the plurality of memory dies.
Mathuriya teaches a heat sink located above the logic die and adapted to remove heat from the logic die and the plurality of memory dies (Fig. 4B, heat sink 315, compute die 402; Col. 13, line 29 - Col. 15, line 64).
Bhushan and Mathuriya are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Bhushan with the teachings of Mathuriya such that a heat sink is located above the logic die and adapted to remove heat from the logic die and the plurality of memory dies. For the purpose of improved thermal characteristics and heat management of the device, as recognized by Mathuriya.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kellam et al. (US Patent No. 12,639,003), Wen et al. (Pub. No. US 20250167077), Chou et al. (Pub. No. US 20120146207 A1), Binkert et al. (US Patent No. 8.064,739), Chang (Pub. No. US 20220310483 A1), and Li et al. (Pub. No. US 20150279431)
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./ Examiner, Art Unit 2897
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