Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claims 1, 2, 6 and 7 are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Ranade (20080227250).
Regarding claim 1, Ranade teaches a method of fabricating an integrated circuit structure, the method comprising:
forming a first silicon body (fig. 5: 100) having a longest dimension along a first direction (par. 8);
forming a second silicon body (fig. 5: 102 + 106) having a longest dimension along the first direction (par. 9);
forming a gate line over the first silicon body and over the second silicon body along a second direction, the second direction orthogonal to the first direction (fig. 11 shows the gate line going into the page and is perpendicular to 100 and 102 + 106),
wherein the gate line has an uppermost surface, and wherein the gate line comprises a high-k gate dielectric layer (fig. 11: 116), and a gate electrode (fig. 11: 118);
forming a trench contact line (fig. 12: 124) over the first silicon body and over the second silicon body along the second direction, the trench contact adjacent to the gate line (see fig. 12), wherein the trench contact is continuous between the first silicon body and the second silicon body, and wherein the trench contact line has an uppermost surface at a same level as the uppermost surface of the gate line (see fig. 12 which shows this configuration); and
forming a dielectric spacer laterally between the trench contact and the gate line (par. 18).
Regarding claim 2, Ranade teaches a method of claim 1, wherein the trench contact is directly adjacent to and in contact with the dielectric spacer (see fig. 11 and 12).
Regarding claim 6, Ranade teaches a method of claim 1, wherein the dielectric spacer comprises silicon and nitrogen (par. 25 and 26).
Regarding claim 7, Ranade teaches a method of claim 1, wherein the high-k gate dielectric layer comprises hafnium and oxygen (par. 13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Ranade as applied to claim 1 above, and further in view of Tsai (20090127610).
Regarding claim 3-5, Ranade teaches a method of claim 1.
Ranade teaches a gate line with spacers, but fails to teach:
the gate line further comprises a dielectric cap layer
the dielectric cap layer is laterally adjacent to the dielectric spacer
the dielectric cap layer comprises silicon carbide
Tsai teaches a gate lines with spacers (fig. 3B) wherein the gate line has spacers on the sides and a cap layer atop and around the spacer, the cap layer being composed SiC (par. 52). It is known in the art that SiC offers a combination of thermal stability, chemical inertness, and mechanical robustness that addresses many challenges in the fabrication of gate lines. The use of cap layers, taught in Tsai, in Ranade would confer these benefits to the device taught in Ranade.
Thus, it would have been obvious to a PHOSITA, at the time of filing, to utilize aforementioned teachings of the prior art(s) in the primary prior art(s) due to aforementioned reason(s).
Allowable Subject Matter
Claims 8-14 allowed.
The following is an examiner’s statement of reasons for allowance: prior art fails to anticipate and obviate limitations mentioned in claim 8. Case in point, prior art fails to teach the temporal ordering of steps mentioned in claim 8.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 15-20 allowed.
The following is an examiner’s statement of reasons for allowance: prior art fails to anticipate and obviate limitations mentioned in claim 15. Case in point, prior art fails to teach the temporal ordering of steps mentioned in claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALEB E HENRY/Primary Examiner, Art Unit 2818
Prosecution Insights