DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 is objected to because of the following informalities: the phrase (emphasis added), “wherein the storage node side-ohmic contact include a metal silicide,” which is grammatically incorrect. Appropriate correction is required.
The examiner believes that the phrase should read: wherein the storage node side-ohmic contact includes a metal silicide.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the active layer" in lines 5, 7, 10, 14, and 17. There is insufficient antecedent basis for this limitation in the claim.
For purposes of examination, the examiner has interpreted “the active layer” in a manner similar to the way that it is defined in claim 1 such that: a horizontally oriented transistor has an active layer comprising a first source/drain region, a second source/drain region, a channel between the first and second source/drain regions, and a gate all-around word line surrounding the channel of the active layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (United States Patent Application Publication No. US 2008/0185648 A1, hereinafter “Jeong”) in view of Chen et al. (United States Patent Application Publication No. US 2004/0166642 A1, hereinafter “Chen”) and further in view of Joshi et al. (USPN 4,216,573, hereinafter “Joshi”).
In reference to claim 1, Jeong discloses a similar device. Fig. 2 and 3 in conjunction with fig. 6, 7, 10D, 11C of Jeong disclose a semiconductor memory device which comprises a horizontally oriented active layer (342, 343, 344, 442, 443, 444) comprising a first end (342, 442), a second end (344, 444), and a channel (343, 443) between the first (342, 442) and second (344, 444) ends. A word line (WL, 354, 454) is over the channel (343, 443) of the active layer (342, 343, 344, 442, 443, 444). Nodes (496a, 496b) are formed on an upper surface and a lower surface of the first end (342, 442) of the active layer (342, 343, 344, 442, 443, 444) respectively. A vertical contact (496c) vertically extends and connects to the first end (342, 442) of the active layer (342, 343, 344, 442, 443, 444) and the nodes (496a, 496b). A bit line (398, 498) is connected to the contact.
Jeong does not disclose that the gate/word line (WL, 354, 454) surrounds the active layer (342, 343, 344, 442, 443, 444). However fig. 6B of Chen discloses the use of a wrap-around gate structure (64) which surrounds the channel/active layer (60). Chen discloses that a wrap-around gate structure provides the benefit of controlling short channel effects (p. 1, paragraph 4) which is desirable in the art (p. 1, paragraph 2). In view of Chen, it would therefore be obvious to implement a gate/word line (WL, 354, 454) which surrounds the channel (343, 443) of the active layer (342, 343, 344, 442, 443, 444) in the Jeong device.
Jeong does not disclose that the nodes (496a, 496b) are formed of doped polysilicon. Jeong also does not disclose that the vertical contact (496c) is formed of a metal silicide. However Joshi discloses that doped polysilicon and metal silicides are known conductive materials (column 15, lines 16-21). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to use doped polysilicon for the nodes (496a, 496b) and a metal silicide for the vertical contact (496c) in the device of Jeong constructed in view of Chen.
With regard to claim 2, in the device of Jeong constructed in view of Chen and Joshi, the active layer (342, 343, 344, 442, 443, 444) further comprises a first source/drain region (342, 442) that is disposed on one side of the channel (343, 443) and is connected to the metal silicide (496c) and the doped polysilicon nodes (496a, 496b). A second source/drain region (344, 444) is disposed on another side of the channel (343, 443).
In reference to claim 3, in the device of Jeong constructed in view of Chen and Joshi, the metal silicide (496c) has a height that fully covers side surfaces of the doped polysilicon nodes (496a, 496b) and the first source/drain region (342, 442).
With regard to claim 4, Jeong discloses that the active layer (342, 343, 344, 442, 443, 444) includes polysilicon (p. 6, paragraphs 62 and 71).
In reference to claim 6, in the device of Jeong constructed in view of Chen and Joshi, the word line/gate (WL, 354, 454 - fig. 2, 3, 6, 7, 10D, 11C of Jeong) wraps entirely around the channel (343, 443 - fig. 2, 3, 6, 7, 10D, 11C of Jeong) such that the channel (343, 443 - fig. 2, 3, 6, 7, 10D, 11C of Jeong) is thinner than the word line/gate (WL, 354, 454 - fig. 2, 3, 6, 7, 10D, 11C of Jeong) in the same manner seen in fig. 6B of Chen.
In reference to claim 7, as noted above with regard to claim 1, the device of Jeong constructed in view of Chen and Joshi uses a wrap-around gate structure which surrounds the channel of the active layer (fig. 6B and p. 1, paragraph 4 of Chen). Chen discloses that the use of a wrap-around gate/word line forms a gate all around transistor structure (p. 1, paragraph 4). Thus the device of Jeong constructed in view of Chen and Joshi meets claim 7.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Chen and further in view of Joshi as applied to claim 1 above and further in view of Xie et al. (USPN 9,847,390 B1, hereinafter “Xie”).
With regard to claim 5, as noted above with regard to claim 1, the device of Jeong constructed in view of Chen and Joshi uses doped polysilicon nodes (496a, 496b - fig. 6, 7, 10D, 11C of Jeong) in contact with the first end of the active layer (342, 343, 344, 442, 443, 444 – fig. 6, 7, 10D, 11C of Jeong). Jeong does not disclose that the nodes (496a, 496b) cover the upper, lower, and side surfaces of the first end (source/drain) of the active layer (342, 343, 344, 442, 443, 444). However Xie discloses the use of a wrap-around contact which is formed over the entire outer surface of the source/drain regions in order to reduce resistance (column 1, lines 43-45) which is desirable in the art (column 4, lines 8-13). In view of Xie, it would therefore be obvious to implement the doped polysilicon nodes in the device of Jeong constructed in view of Chen and Joshi such that they cover the upper, lower, and side surfaces of the first end (source/drain) of the active layer.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Chen and further in view of Joshi as applied to claim 1 above and as further evidenced by Reznicek et al. (United States Patent Application Publication No. US 2022/0093794 A1, hereinafter “Reznicek”).
With regard to claim 8, fig. 6, 7, 10D, 11C of Jeong disclose electrically connecting the second end (344, 444) to another transistor. Jeong discloses that the transistors store the data in the form of a charge using the floating-body effect (p. 1, paragraphs 8 and 9). Reznicek discloses that using the floating-body effect as a way of storing data or charge means that the transistor body functions as a capacitor (p. 1, paragraph 2). Thus the device of Jeong constructed in view of Chen and Joshi meets claim 8.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Chen and further in view of Joshi and as further evidenced by Reznicek.
In reference to claim 11, Jeong discloses a similar device. Fig. 2 and 3 in conjunction with fig. 6, 7, 10D, 11C of Jeong disclose a semiconductor memory device which comprises a horizontally oriented transistor having an active layer (342, 343, 344, 442, 443, 444) comprising a first source/drain region (342, 442), a second source/drain region (344, 444), a channel (343, 443) between the first (342, 442) and second (344, 444) source/drain regions. A gate (WL, 354, 454) is over the channel (343, 443) of the active layer (342, 343, 344, 442, 443, 444). First nodes (496a, 496b) are formed on an upper surface and a lower surface of the first source/drain region (342, 442) of the active layer (342, 343, 344, 442, 443, 444) respectively. A first vertical contact (496c) vertically extends and connects to the first source/drain region (342, 442) of the active layer (342, 343, 344, 442, 443, 444) and the first nodes (496a, 496b). A bit line (398, 498) is connected to the first vertical contact (496c). Second nodes (note unlabeled structures with the same structure as (496a, 496b) to the right of (344, 444)) are formed on an upper surface and a lower surface of the active layer (342, 343, 344, 442, 443, 444). A second vertical contact (note unlabeled structure with the same structure as (496c) to the right of (344, 444)) vertically extends and connects to the second source/drain region (344, 444) of the active layer (342, 343, 344, 442, 443, 444) and the second nodes (note unlabeled structures with the same structure as (496a, 496b) to the right of (344, 444)). Fig. 6, 7, 10D, 11C of Jeong discloses electrically connecting the second end (344, 444) to another transistor. Jeong discloses that the transistors store the data in the form of a charge using the floating-body effect (p. 1, paragraphs 8 and 9). Reznicek discloses that using the floating-body effect as a way of storing data or charge means that the transistor body functions as a capacitor (p. 1, paragraph 2). Thus the device of Jeong meets the limitation that a capacitor is connected to the second vertical contact (note unlabeled structure with the same structure as (496c) to the right of (344, 444)).
Jeong does not disclose that the gate/word line (WL, 354, 454) surrounds the channel (343, 443) of the active layer (342, 343, 344, 442, 443, 444). However fig. 6B of Chen discloses the use of a wrap-around gate structure (64) which surrounds the channel/active layer (60). Chen discloses that such a gate structure provides the benefit of controlling short channel effects (p. 1, paragraph 4) which is desirable in the art (p. 1, paragraph 2). In view of Chen, it would therefore be obvious to implement a gate/word line (WL, 354, 454) which surrounds the channel (343, 443) of the active layer (342, 343, 344, 442, 443, 444) in the Jeong device.
Jeong does not disclose that the first (496a, 496b) and second (note unlabeled structures with the same structure as (496a, 496b) to the right of (344, 444)) nodes are formed of doped polysilicon. Jeong also does not disclose that the first vertical contact (496c) and the second vertical contact (note unlabeled structure with the same structure as (496c) to the right of (344, 444)) are formed of a metal silicide. However Joshi discloses that doped polysilicon and metal silicides are known conductive materials (column 15, lines 16-21). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to use doped polysilicon for the first node (496a, 496b) and the second node (note unlabeled structures with the same structure as (496a, 496b) to the right of (344, 444)). Furthermore, in view of the above, it would therefore be obvious to use a metal silicide for the first vertical contact (496c) and the second vertical contact (note unlabeled structure with the same structure as (496c) to the right of (344, 444)) in the device of Jeong constructed in view of Chen.
Allowable Subject Matter
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims AND if the language of claim 10 is corrected (see above section titled Claims Objections).
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a memory device with a horizontally active layer with a channel surrounded by a word line with doped polysilicon nodes on the upper and lower surfaces of a first end of the active layer such that a metal silicide vertically extends and connects the first end of the active layer and the doped polysilicon nodes while being connected to a bit line in combination with the specific storage contact nodes and storage node side-ohmic contact structures described by the applicant in claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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