DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/03/2024 and 01/04/2025 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Umeda (US 2011/0272740 A1), and further in view of Mizue (US 2019/0181232A1).
Regarding claim 1, Umeda teaches a semiconductor in fig. 1 comprising:
a channel layer (103) disposed on a substrate (101);
a barrier layer (104) disposed on the channel layer (103);
a gate structure (106) disposed on the barrier layer (104), the gate structure (106)comprising a main portion (refer to center/body portion of 106) and a head portion (refer to outer portion of 106) adjacent to an end of the main portion (refer to center/body portion of 106), wherein the head portion comprises nitrogen ions, oxygen ions, fluoride ions, or argon ions (see par. 95); and
a source electrode (107) and a drain electrode (108) disposed on the barrier layer (104) and disposed at opposite sides of the gate structure (see fig. 1 or fig. 2).
Umeda does not teach “a width of the head portion is greater than a width of a center of the main portion”
Mizue teaches the same field of an endeavor wherein a width of the head portion (33a) is greater than a width of a center of the main portion (33b) (see fig. 1).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a width of the head portion is greater than a width of a center of the main portion as taught by Mizue in the teaching of Umeda because of a wider head portion of the gate electrode functions as the landing area for an external connection by bonding wires while the main portion of the gate electrode is narrower to minimize the physical space it occupies and reduce parasitic capacitance which preserves high frequency performance.
Regarding claim 2, Umeda and Mizue teach all the limitations of the claimed invention for the same field of an endeavor. Besides, Mizue teaches the semiconductor device comprises: an active area (A1) comprising the main portion (33b) of the gate structure (see par. 56); and an isolation area (B12) comprising the head portion of the gate structure (33a) (see par. 56).
It should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 2 is directed to a device, the method of forming “the active area … and the isolation area” are not germane to the issue of patentability of the device itself. Therefore, the limitation of “…the active area is not processed by an plasma bombard process… and the isolation area is processed by an plasma bombard process" stated in claim 2 has not been given any patentable weight. MPEP 2113 [R-1].
Regarding claim 4, Umeda and Mizue teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 1 of Mizue teaches a sum of a width of a head portion of the source electrode, the width of the head portion of the gate structure, a width of a head portion of the drain electrode, and spacings (refer to the below notation Ws1) therebetween is equal to a sum of a width of a center of a main portion of the source electrode, the width of the center of the main portion of the gate structure, a width of a center of a main portion of the drain electrode, and spacings therebetween (refer to the below notation Ws2).
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Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Mizue as applied to claim 1 above, and further in view of Cheng (CN 209675293).
Regarding claim 3, Umeda and Mizue teach all the limitations of the claimed invention for the same reasons as set forth above except for portions of the barrier layer and the channel layer at the isolation area comprise lattice defects.
Cheng teaches portions of the barrier layer and the channel layer at the isolation area comprise lattice defects (NOTE: because: the fluoride ion cause lattice damage to the nitride material).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include portions of the barrier layer and the channel layer at the isolation area comprise lattice defects as taught by Cheng in the combined teaching of Umeda and Mizue in order to form an enhancement mode device structure.
Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Umeda and further in view of Hanson (US 20210296452).
Regarding claim 5, Umeda teaches a semiconductor in fig. 1 comprising:
a channel layer (103) disposed on a substrate (101);
a barrier layer (104) disposed on the channel layer (103);
a gate structure (106) disposed on the barrier layer (104), the gate structure (106)comprising a main portion (refer to center/body portion of 106) and two head portions (refer to outer portions of 106) adjacent to an end of the main portion (refer to center/body portion of 106), wherein the head portion comprises nitrogen ions, oxygen ions, fluoride ions, or argon ions (see par. 95); and
a source electrode (107) and a drain electrode (108) disposed on the barrier layer (104) and disposed at opposite sides of the gate structure (see fig. 1 or fig. 2), wherein the gate structure, the source electrode, and the drain electrode are extended in a first direction (refer to y-axis), lengths of the head portions and the main portion are measured in the first direction (refer to y-axis), the widths of the head portions and the width of the center of the main portion are measured in a second direction (refer to x-axis), wherein the second direction is perpendicular to the first direction.
Umeda does not teach “wherein a width of each of the head portions is greater than a width of a center of the main portion.”
Hanson teaches the same field of an endeavor wherein a gate structure (140) comprising a main portion (170) and two head portions (refer to gate connected field plate 145 and gate pad 185) wherein a width of each of the head portions (185 and 145) is greater than a width of a center of the main portion (refer to 170) (see figs. 1B), wherein the gate structure, the source electrode, and the drain electrode are extended in a first direction (refer to y axis), lengths of the head portions and the main portion are measured in the first direction (refer to y-axis), the widths of the head portions and the width of the center of the main portion are measured in a second direction (refer to x-axis), wherein the second direction is perpendicular to the first direction.
Thus, it would have been obvious to one having ordinary skills in the art to include wherein a width of each of the head portions is greater than a width of a center of the main portion as taught by Hanson in the teaching of Umeda because a gate pad functions as the landing areas for an external connections and a wider shape of gate connected filed plate is used to broaden the depletion region and reshapes the electric field peak, reducing the maximum filed strength at the gate edge. Meanwhile, the main portion of the gate electrode is narrower to minimize the physical space it occupies and reduce parasitic capacitance which preserves high frequency performance.
Regarding claim 8, Umeda and Hanson teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 1B Hanson shows the head portions of the gate structures (refer to the extension of 185 and 145 are protruding closer to source contact 160 than the body 170) are extended towards the source electrode, and the head portions of the gate structure (145 and 185) are located at opposite ends of a main portion of the source electrode (refer to body/center of source electrode 160), in the first direction (refer to y-axis).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the head portions of the gate structures are extended towards the source electrode, and a width of a head portion of the source electrode is smaller than a width of a center of a main portion of the source electrode.”
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the head portions of the gate structures are extended towards the drain electrode, and a width of a head portion of the drain electrode is smaller than a width of a center of a main portion of the drain electrode.”
Reference 1: Umeda (US 2011/0272740 A1)
Reference 2: Shih (US 2023/0369480 A1)
Regarding claim 9, Umeda teaches a semiconductor in fig. 1 comprising:
a channel layer (103) disposed on a substrate (101);
a barrier layer (104) disposed on the channel layer (103);
a gate structure (106) disposed on the barrier layer (104), the gate structure (106)comprising a main portion (refer to center/body portion of 106) and two head portions (refer to outer portions of 106) adjacent to an end of the main portion (refer to center/body portion of 106), wherein the head portion comprises nitrogen ions, oxygen ions, fluoride ions, or argon ions (see par. 95), wherein a width of each of the head portions is equal to a width of a center of the main portion; and
a source electrode (107) and a drain electrode (108) disposed on the barrier layer (104) and disposed at opposite sides of the gate structure (see fig. 1 or fig. 2).
Umeda does not teach “wherein a width of each of the head portions is greater than a width of a center of the main portion”
Shih teaches the same field of an endeavor wherein gate terminus (60) comprises a width of each of the head portions is greater than a width of a center of the main portion (see figs. 2 and 3), wherein the gate structure, the source electrode, and the drain electrode are extended in a first direction (refer to, lengths of the head portions and the main portion are measured in the first direction (refer to vertical direction or y-axis), the widths of the head portions and the width of the center of the main portion are measured in a second direction (refer to horizontal direction or x-axis), wherein the second direction is perpendicular to the first direction.
However, Umeda, Shih do not teach “performing a plasma bombard process using the patterned photoresist as a mask, to inject ions into the isolation area thereby forming an isolation region in the barrier layer and the channel layer, wherein performing the plasma bombard process comprises forming lattice defects in portions of the barrier layer and the channel layer at the isolation area” (cited in claim 9).
Claims 9-10 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 9, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a semiconductor device comprising: “performing a plasma bombard process using the patterned photoresist as a mask, to inject ions into the isolation area thereby forming an isolation region in the barrier layer and the channel layer, wherein performing the plasma bombard process comprises forming lattice defects in portions of the barrier layer and the channel layer at the isolation area” in combination of all of the limitations of claim 9. Claim 10 includes all of the limitations of claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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