DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 3302, 3304, 3308, 3310 and 3302 of fig. 33-37. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a metal region contacting with a top surface and a sidewall of the heavily doped region” of claim 7, Note, no reference in the drawings is clearly identifiable as comprising metal and illustrated as contacting with a top surface and a sidewall of the heavily doped region must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 15 is objected to because of the following informalities: Claim 15 recites “a gate conductive layer and a gate dielectric layer across over the single convex structure”. This is not grammatically correct. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6, 8-13 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20110156136 A1 Koichi hereafter “Koichi”.
Claim 1 Koichi teaches A transistor structure (embodied fig. 1-4) comprising:
a body (101 fig. 2) with a single convex structure [sufficiently illustrated fig. 2], wherein the convex structure is made of a first semiconductor material [disclosed with sufficient specificity “semiconductor substrate” paragraph 0014], and a trench (TR fig. 2) is formed in the single convex structure;
a gate structure (111 fig. 2) with a gate conductive layer (111g fig. 2) and a gate dielectric layer (111z fig. 2), wherein the gate conductive layer is across over the single convex structure, and a portion of the gate conductive layer is filled in the trench [sufficient];
a source region (comprising 112Hs and 112Ls fig. 4) contacting with a first end (Y3 and/or -X fig. 4) of the single convex structure; and
a drain region (comprising 112Hd and 112 Ld fig. 4) contacting with a second end (Y4 and/or +X fig. 4) of the single convex structure;
wherein a ratio of ON current (Ion) to Off current (Ioff) of the transistor structure is not less than 106 [This property limitation is met under MPEP 2112.01 the structure and/or composition are substantially identical as claimed and/or disclosed].
Claim 2 Koichi teaches as shown above the transistor structure in claim 1, wherein the ratio of Ion/Ioff of the transistor structure is around 1~10×106 [This property limitation is met under MPEP 2112.01 the structure and/or composition are substantially identical as claimed and/or disclosed].
Claim 6 Koichi teaches as shown above the transistor structure in claim 1, further comprising:
a first concave [see annotation below] accommodating the source region;
a second concave [see annotation below] accommodating the drain region; and
wherein sidewalls of the first concave and sidewalls of the second concave are surrounded by a STI region (200 fig. 4)[sufficiently illustrated fig. 4]; an edge of the source region contacts with the two vertical thin bodies [CV fig. 1-4], and an edge of the drain region contacts with the two vertical thin bodies [sufficiently illustrated fig. 1-4, note in view of fig. 2 the drain as illustrated fig. 3 contacts at least two thin of the illustrated vertical thin bodies].
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Koichi annotated fig. 3: highlighting a cross section across a vertical thin body and a first concave and second concave
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Koichi annotated fig. 2: highlighting the location of the source/drain regions in view of fig. 1, 3 and 4
Claim 8 Koichi teaches a transistor structure (fig. 1-4) comprising:
a body (101 fig. 2 and 4) with a convex structure [sufficiently illustrated fig. 2 and 4] which has an original surface [the top most surface of 101 best illustrated illustrated fig. 2], wherein the body is made of a semiconductor material [disclosed with sufficient specificity in “semiconductor substrate” paragraph 0014], and the convex structure has multiple conductive channels (101c fig. 1-4);
a source region (comprising 112Hs and 112 Ls fig. 1-4) contacting with a first end of the convex structure (Y1/Y3, -X end fig. 3 or 4);
a drain region (comprising 112Hd and 112Ld fig. 1-4) contacting with a second end of the convex structure (Y2/Y4, +X end fig. 3 or 4); and
a gate region (comprising 111g and 111z fig. 1-4) with a gate conductive layer (111g fig. 1-4), wherein the gate conductive layer is across over the convex structure [best illustrated fig. 2], a first portion of the gate conductive layer is in the convex structure and under the original surface [sufficiently illustrated fig. 2], and a second portion of the gate conductive layer is above the original surface [sufficiently illustrated fig. 2];
wherein a subthreshold slope (SS) of the transistor structure is not greater than 74 [This electrical property limitation of the transistor is met under MPEP 2112.01 the structure and/or composition are substantially identical as claimed and/or disclosed].
Claim 9 Koichi teaches as shown above the transistor structure in claim 8, wherein the SS of the transistor is between 71~74 [This electrical property limitation of the transistor is met under MPEP 2112.01 the structure and/or composition are substantially identical as claimed and/or disclosed].
Claim 10 Koichi teaches as shown above the transistor structure in claim 8, wherein a length of the second portion of the gate conductive layer is longer than that of the first portion of the gate conductive layer [sufficiently illustrated fig. 2, see annotation below], a trench (TR fig. 2) formed in the convex structure and between the first end and the second end, and the first portion of the gate conductive layer is filled in the trench [sufficiently illustrated fig. 2].
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Annotated fig. 2: highlighting a length of a second portion and a length of a first portion
Claim 11 Koichi teaches as shown above the transistor structure in claim 10, wherein the convex structure comprises two thin bodies (CV fig. 2, met under broadest reasonable interpretation wherein CV is at least two sub-bodies thinner that the main body)extending upward [sufficiently illustrated fig. 2], and each thin body comprises two conductive channels along sidewalls of the thin body [sufficiently illustrated fig. 2, see annotation below. This limitation is met under broadest reasonable interpretation and/or MPEP 2112.01], and the trench filled with the first portion of the gate conductive layer is between the two thin bodies [sufficiently illustrated fig. 2].
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Koichi annotated fig. 2: highlighting channels
Claim 12 Koichi teaches as shown above the transistor structure in claim 11, further comprising a gate dielectric (111z fig. 2 and 4) layer being across over the convex structure, wherein the first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench [sufficiently illustrated fig. 2], and the gate conductive layer is surrounded by the gate dielectric layer along four sidewalls and the bottom of the trench [at least for sidewalls and the bottom of the trench illustrated fig. 2].
Claim 13 Koichi teaches as shown above the transistor structure in claim 12, wherein right under the bottom of the trench is the semiconductor material of the body [sufficiently illustrated fig. 2], and the gate dielectric layer along the bottom of the trench directly contacts with the semiconductor material of the body [sufficiently illustrated fig. 2].
Claim 15 Koichi teaches a transistor structure comprising:
a semiconductor body (101 fig. 1-4) with a single convex structure [sufficiently illustrated fig. 1-4];
a gate conductive layer (111g fig. 1-4) and a gate dielectric layer (111z fig. 1-4 ) across over the single convex structure [best illustrated fig. 2], wherein the single convex structure comprises at least 4 upward extending conductor-oxide-semiconductor interfaces [best illustrated fig. 2];
a source region (112s fig. 1-4) contacting with a first end (Y1/Y3, -X end fig. 3/4) of the single convex structure; and
a drain region (112d fig. 1-4) contacting with a second end (Y2/Y4, +X end fig. 3/4) of the single convex structure;
wherein Ion of the transistor structure is not less than 90 uA [This property limitation is met under MPEP 2112.01 the structure and/or composition are substantially identical as claimed and/or disclosed].
Claim 16 Koichi teaches as shown above the transistor structure in claim 15, wherein Ioff of the transistor structure is not greater than 90 uA [This property limitation is met under MPEP 2112.01 the structure and/or composition are substantially identical as claimed and/or disclosed].
Claim 17 Koichi teaches as shown above the transistor structure in claim 16, wherein the single convex structure comprises two upward extending thin bodies [at least two CV fig. 2], each upward extending thin body comprises two upward extending conductor-oxide-semiconductor interfaces [sufficiently illustrated fig. 2, disclosed as “metallic materials” 111g [Paragraph 0064]-“Oxides” 111z [paragraph 0065]-“semiconductor substrate” 101], and a trench [TR fig. 2] is formed in the single convex structure to separate the two upward extending thin bodies [sufficiently illustrated fig. 2].
Claim 18 Koichi teaches as shown above the transistor structure in claim 17, wherein the at least 4 upward extended conductor-oxide-semiconductor interfaces are horizontally shifted with each other, and no STI region is between the two upward extending bodies [sufficiently illustrated fig. 2 they are shifted along the X direction].
Claim 19 Koichi teaches as shown above the transistor structure in claim 15, wherein a threshold voltage (Vth) of the transistor structure is between 330mv~360mv [This property limitation is met under MPEP 2112.01 the structure and/or composition are substantially identical as claimed and/or disclosed].
Claim 20 Koichi teaches as shown above the transistor structure in claim 15, further comprising:
a spacer (SW fig. 1-4) next to the gate conductive layer and being across over a top surface and sidewalls of the single convex structure [sufficiently illustrated fig. 3 and fig. 3].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 are rejected under 35 U.S.C. 103 as being unpatentable over Koichi as applied to the claims above, and further in view of US 7189617 B2 Slesazeck hereafter “Slesazeck”.
Claim 3-4 Koichi teaches as shown above the transistor structure in claim 1, wherein the convex structure comprises a first outer sidewall [see annotation below] and a second outer sidewall [see annotation below], the convex structure further comprises a first inner sidewall [see annotation below] and a second inner sidewall [see annotation below] in the trench; wherein a length of the first inner sidewall or the second inner sidewall is shorter than that of the first outer sidewall or the second outer sidewall [sufficiently illustrated fig. 2].
Koichi does not teach the first outer sidewall and the second outer sidewall covered by the gate conductive layer.
Slesazeck teaches a first outer sidewall [see annotation below] and a second outer sidewall [see annotation below] covered by a gate conductive layer (5a of 30’ fig. 7B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Koichi in view of Slesazeck such that ‘the first outer sidewall and the second outer sidewall covered by the gate conductive layer’.
A person of ordinary skill in the art would have been motivated to make this modification to improve the control of the gate over the channel region [ disclosed in Slesazeck Column 5 lines 7-11 “By providing these under-etching areas 5a, the control of the gate over the channel region is improved by the tri-gate arrangement, because the gate can be extended to below the corners at the bottom U”].
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Koichi Annotated fig. 2: highlighting sidewalls
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Slesazeck Annotated fig. 4B: highlighting outer sidewalls
Claim 4 Koichi teaches as shown above the transistor structure in claim 1, wherein a bottom surface and sidewalls of the trench are covered by the gate dielectric layer [sufficiently illustrated fig. 2],
Koichi does not teach a bottom of the gate conductive layer outside the single convex structure is lower than that of the portion of the gate conductive layer is filled in the trench.
Slesazeck teaches under-etching areas (5a fig. 7a-7b) wherein a gate extends (30’ and 20 fig. 7a-7b) to below the corners at the bottom of a trench (U fig. 7a-7b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Koichi in view of Slesazeck such that “a bottom of the gate conductive layer outside the single convex structure is lower than that of the portion of the gate conductive layer is filled in the trench”.
A person of ordinary skill in the art would have been motivated to make this modification to improve the control of the gate over the channel region [ disclosed in Slesazeck Column 5 lines 7-11 “By providing these under-etching areas 5a, the control of the gate over the channel region is improved by the tri-gate arrangement, because the gate can be extended to below the corners at the bottom U”].
Claims 5 are rejected under 35 U.S.C. 103 as being unpatentable over Koichi as applied to the claims above, and further in view of US 20240312997 A1 Lin hereafter “Lin”.
Claim 5 Koichi teaches as shown above the transistor structure in claim 1, wherein the single convex structure comprises two vertical thin bodies [see annotation below, illustrated fig. 4], and the gate dielectric layer is disposed between the gate conductive layer and the two vertical thin bodies [sufficiently illustrated fig. 4], and
Koichi does not teach a width of one vertical thin body is not greater than 3nm.
Lin teaches an excessive channel width may result in weaker gate control [sufficiently disclosed paragraph 0029].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Koichi in view of Lin such that “a width of one vertical thin body is not greater than 3nm”.
A person of ordinary skill in the art would have been motivated to make this modification to as a part of routine optimization of the result affected variable of gate control [See MPEP 2144.05] and/or to avoid an excessive channel width.
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Koichi annotated fig. 5: highlighting two vertical thin bodies
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koichi as applied to the claims above, and further in view of US 20130105791 A1 Honda et al hereafter “Honda”.
Claim 7 Koichi teaches the transistor structure in claim 6, wherein the source region comprises:
an LDD region (112Ls fig. 4) contacting with the two vertical thin bodies [sufficiently illustrated fig. 4];
a heavily doped region (112Hs fig. 4) laterally extending from the LDD region [sufficiently illustrated fig. 4]; and
Koichi does not teach a metal region contacting with a top surface and a sidewall of the heavily doped region.
Honda teaches a metal region (114a/114b fig. 1B) contacting with a top surface and a sidewall of source/drain regions (106c/106b fig. 1B) [sufficiently illustrated fig. 1B].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Koichi in view of Honda such that “a metal region contacting with a top surface and a sidewall of the heavily doped region”.
A person of ordinary skill in the art would have been motivated to make this modification to electrically address the source region with improved contact resistance, improve the performance of the transistor, and improve the threshold voltage of the transistor [sufficiently disclosed paragraph 0182 Honda].
Claim 14 are rejected under 35 U.S.C. 103 as being unpatentable over Koichi as applied to the claims above, and further in view of US 20170062613 A1 Sung et al here after “Sung”
Claim 14 Koichi teaches as shown above the transistor structure in claim 13,
Further comprising a STI layer [200 fig. 2] surrounding sidewalls of the convex structure.
Koichi does not teach an isolation wall clamping sidewalls of the convex structure, nor the STI layer surrounding the isolation wall.
Sung teach an isolation wall (132 and 134 fig, 2) clamping sidewalls of a convex structure (FA fig. 2), and a STI layer (112D fig. 2) surrounding the isolation wall [sufficiently illustrated fig. 2]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Koichi in view of Sung such that “an isolation wall clamping sidewalls of the convex structure, and the STI layer surrounding the isolation wall”.
A person of ordinary skill in the art would have been motivated to make this modification to further insulate the convex structure [sufficiently disclosed by “insulating liner” paragraph 0057 Sung] and/or improve carrier mobility in the channel regions by applying stress to the convex structure[sufficiently disclosed Paragraph 0061 Sung].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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