Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-12 are rejected under 35 U.S.C. 102(a1) as being anticipated by Hsieh et al. (US 10,062,648; hereinafter Hsieh).
Regarding claim 1, Hsieh, in fig. 25, discloses a packaging structure of an optical communication module, comprising: a first redistribution structure 120, wherein a distribution layer 120 is disposed in the first redistribution structure 120 (fig. 4); a plastic packaging structure 130 (fig. 5), wherein the plastic packaging structure 130 wraps surfaces of the first redistribution structure 120 other than an upper surface, the plastic packaging structure 130 on a periphery of the first redistribution structure 120 is provided with at least one through via 112, and each of the at least one through via 112 penetrates an upper surface and a lower surface of the plastic packaging structure 130; and a first chip 118 and a second chip 118, wherein the first chip 118 and the second chip 118 are disposed above the first redistribution structure 120 and the plastic packaging structure 130, the first chip 118 is connected to the second chip 118 by using the distribution layer 130, and at least a part of lead-out ends of the first chip and at least a part of lead-out ends of the second chip are led from the upper surface of the plastic packaging structure 130 to the lower surface by using the at least one through via 112 connect with a conductive line 162/166 on a printed circuit board 400.
Regarding claim 2, Hsieh discloses wherein the plastic packaging structure 130 comprises a plurality of through vias 112; the first chip 118 is disposed above the upper surface of the first redistribution structure 120 and the upper surface of the plastic packaging structure 130 by using a plurality of first micro bumps, the first chip 118 is connected to a conductive line in the distribution layer 120 by using a second micro bump in the plurality of first micro bumps, and the first chip 118 is connected to a first through via 112 in the plurality of through vias 112 by using a third micro bump in the plurality of first micro bumps; and the second chip 118 is disposed above the upper surface of the first redistribution structure 120 and the upper surface of the plastic packaging structure 130 by using a plurality of fourth micro bumps, the second chip 118 is connected to the conductive line in the distribution layer 120 by using a fifth micro bump in the plurality of fourth micro bumps, and the second chip 118 is connected to a second through via 112 in the plurality of through vias 112 by using a sixth micro bump in the plurality of fourth micro bumps (fig. 25).
Regarding claim 3, Hsieh discloses wherein a second redistribution structure 160 is further disposed on the upper surface of the first redistribution structure 120 and the upper surface of the plastic packaging structure 130; and the first chip 118 is connected to the second chip 118 by using the first redistribution structure 120 and the second redistribution structure 160 (fig. 25).
Regarding claim 4, Hsieh discloses wherein the first chip 118 comprises a port configured to couple a fiber array unit; and the port is disposed on a first surface or a second surface of the first chip, the first surface is a surface that is close to the plastic packaging structure 130, and the second surface is a surface that is away from the plastic packaging structure 130 (fig. 25).
Regarding claim 5, Hsieh discloses wherein, when the port configured to couple the fiber array unit is disposed on the first surface of the first chip 118, an insulation material 130 is filled between a region of the first chip 118 other than a region in which the port is disposed, and the first redistribution structure 120 and the plastic packaging structure 130; and the insulation material 130 is filled between the second chip 118 and both of the first redistribution structure 120 and the plastic packaging structure 130 (fig. 25).
Regarding claim 6, Hsieh discloses wherein, when the port configured to couple the fiber array unit is disposed on the second surface of the first chip 118, surfaces of the first chip 118 and the second chip 118 other than a surface away from the first redistribution structure 120 are wrapped by a plastic packaging material 130 (fig. 25).
Regarding claim 7, Hsieh, in fig. 25, discloses an optical communication device (col. 4, lines 57-67), wherein the optical communication device comprises a printed circuit board 400 and a packaging structure 200 of an optical communication module; wherein the optical communication module comprising: a first redistribution structure 120, wherein a distribution laver 120 is disposed in the first redistribution structure 120; a plastic packaging structure 130, wherein the plastic packaging structure 130 wraps surfaces of the first redistribution structure 120 other than an upper surface, the plastic packaging structure 130 on a periphery of the first redistribution structure 120 is provided with at least one through via 112, and each of the at least one through via 112 penetrates an upper surface and a lower surface of the plastic packaging structure 130; and a first chip 118 and a second chip 118, wherein the first chip 118 and the second chip 118 are disposed above the first redistribution structure 120 and the plastic packaging structure 130, the first chip 118 is connected to the second chip 118 by using the distribution laver 120, and at least a part of lead-out ends of the first chip 118 and at least a part of lead-out ends of the second chip 118 are led from the upper surface of the plastic packaging structure 130 to the lower surface by using the at least one through via 112, to connect with a conductive line 162 on a printed circuit board 400, wherein at least one bump 166 is disposed on a lower surface of the plastic packaging structure 130, and the at least a part of lead-out ends of the first chip 118 and the at least a part of lead-out ends of the second chip 118 are correspondingly connected to the at least one through via 112 by using the at least one bump 166; the conductive line 162 is disposed on the printed circuit board 400; and the at least one bump 166 is welded to the printed circuit board 400, and the first chip 118 and the second chip 118 are connected to the conductive line 162 on the printed circuit board 400 by using the at least one through via 112 and the at least one bump 166.
Regarding claim 8, Hsieh, in fig. 25, discloses a production method of a packaging structure of an optical communication module, comprising: producing a distribution layer 120 in a silicon crystal, to form a first redistribution structure 120; forming a plastic packaging structure 130 on a periphery of the first redistribution structure 120, wherein the plastic packaging structure 120 wraps surfaces of the first redistribution structure 120 other than an upper surface; forming at least one through via 112 in the plastic packaging structure 130 on the periphery of the first redistribution structure 120, wherein each of the at least one through via 112 penetrates an upper surface and a lower surface of the plastic packaging structure 130; and disposing a first chip 118 and a second chip 118 above the first redistribution structure 120 and the plastic packaging structure 130, wherein the first chip 118 is connected to the second chip 118 by using the distribution layer 120, and a part of lead-out ends of the first chip 118 and a part of lead-out ends of the second chip 118 are led from the upper surface of the plastic packaging structure 130 to the lower surface by using the at least one through via 112, to connect with a conductive line 162 on a printed circuit board 400.
Regarding claim 9, Hsieh discloses wherein the disposing of the first chip 118 and the second chip 118 above the first redistribution structure 120 and the plastic packaging structure 130 comprises: disposing the first chip 118 above the upper surface of the first redistribution structure 120 and the upper surface of the plastic packaging structure 130 by using a plurality of first micro bumps, wherein the first chip 118 is connected to a conductive line 120 in the distribution layer 120 by using a second micro bump in the plurality of first micro bumps, and the first chip 118 is connected to a first through via 112 in the plurality of through vias 112 by using a third micro bump in the plurality of first micro bumps; and disposing the second chip 118 above the upper surface of the first redistribution structure 120 and the upper surface of the plastic packaging structure 130 by using a plurality of fourth micro bumps, wherein the second chip 118 is connected to the conductive line 120 in the distribution layer 120 by using a fifth micro bump in the plurality of fourth micro bumps, and the second chip 118 is connected to a second through via 112 in the plurality of through vias 112 by using a sixth micro bump in the plurality of fourth micro bumps (fig. 25).
Regarding claim 10, Hsieh discloses wherein the disposing of the first chip 118 and the second chip 118 above the first redistribution structure 120 and the plastic packaging structure 130 comprises: forming a second redistribution structure 160 on the upper surface of the first redistribution structure 120 and the upper surface of the plastic packaging structure 130; and disposing the first chip 118 and the second chip 118 above the second redistribution structure 160, wherein the first chip 118 is connected to the second chip 118 by using the first redistribution structure 120 and the second redistribution structure 160 (fig. 25).
Regarding claim 11, Hsieh discloses wherein the first chip 118 comprises a port configured to couple a fiber array unit, and when the port is disposed on a first surface of the first chip 118 that is close to the plastic packaging structure 130, the production method further comprises: filling an insulation material at bottoms of the first chip 118 and the second chip 118, and on the first redistribution structure 120 and the plastic packaging structure 130, wherein the insulation material does not cover a region in which the port is located (fig. 25).
Regarding claim 12, Hsieh discloses wherein the first chip 118 comprises a port configured to couple a fiber array unit, and when the port is disposed on a second surface of the first chip 118 that is away from the plastic packaging structure 130, the production method further comprises: forming a plastic packaging material 130 around the first chip 118 and the second chip 118, wherein the plastic packaging material 130 wraps surfaces of the first chip 118 and the second chip 118, except for a surface away from the first redistribution structure 120; and polishing and etching a back surface of the first chip 118 to expose the port (fig. 25).
Conclusion
2. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818
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