DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-13, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishimura et al. (2017/143126, hereafter Nishimura).
Regarding claim 1, Nishimura discloses a semiconductor device comprising: a chip (A1, Fig. 2) that has a main surface (11, Fig. 2); a main surface electrode (3, Fig. 2) that is arranged on the main surface; a terminal electrode (41, Fig. 2) that is arrange on the main surface electrode; a sealing insulator (6, Fig. 2) that covers a periphery of the terminal electrode on the main surface such as to expose a part of the terminal electrode; and a terminal film (51, Fig. 2) that covers the terminal electrode.
Regarding claim 2, Nishimura discloses a semiconductor device wherein the terminal (51) film is thinner than the terminal electrode (41) (Fig. 2).
Regarding claim 3, Nishimura discloses a semiconductor device wherein the terminal electrode (41) is thicker than the main surface electrode (3), and the sealing insulator (6) is thicker than the main surface electrode (Fig. 2).
Regarding claim 5, Nishimura discloses a semiconductor device wherein the sealing insulator (6) includes a thermosetting resin (par. 0072).
Regarding claim 6, Nishimura discloses a semiconductor device wherein the terminal film (51) includes at least one of an Ag-based metal film, an Al-based metal film, a Cu-based metal film, an Ni-based metal film, a Pd-based metal film, and an Au-based metal film (par. 0077).
Regarding claim 7, Nishimura discloses a semiconductor device wherein the terminal film (51) has a laminated structure that includes an Ni-based metal film, a Pd-based metal film, and an Au-based metal film that are laminated in that order from the terminal electrode side (par. 0077).
Regarding claim 8, Nishimura discloses a semiconductor device wherein the terminal film (51) has a laminated structure that includes an Ni-based metal film and an Au-based metal film that are laminated in that order from the terminal electrode side (par. 0077).
Regarding claim 9, Nishimura discloses a semiconductor device wherein the terminal electrode (41) is erected in a columnar shape in cross-sectional view (Fig. 2).
Regarding claim 10, Nishimura discloses a semiconductor device wherein the terminal electrode (41) includes a Cu-based metal (par. 0073).
Regarding claim 11, Nishimura discloses a semiconductor device wherein the terminal electrode (41) has a terminal surface (410) and a terminal side wall (41 side), the sealing insulator (6) exposes the terminal surface and covers the terminal side wall, and the terminal film (51) covers the terminal surface (Fig. 2).
Regarding claim 12, Nishimura discloses a semiconductor device wherein the sealing insulator (6) has an insulating main surface (63) that forms a single flat surface with the terminal surface (410), and the terminal film (51) has a portion that covers the insulating main surface (Fig. 2).
Regarding claim 13, Nishimura discloses a semiconductor device wherein the chip (A1) has a side surface, and the sealing insulator (6) has an insulating side wall that forms a single flat surface with the side surface (Fig. 2).
Regarding claim 20, Nishimura discloses a semiconductor device wherein the chip (A1) includes a monocrystal of a wide bandgap semiconductor (par. 0051).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura in view of Hikasa (2023/0343868, hereafter Hikasa).
Regarding claim 4, Nishimura fails to disclose a semiconductor wherein the terminal electrode is thicker than the chip, and the sealing insulator is thicker than the chip.
However, Hikasa teaches a semiconductor wherein the terminal electrode (75) is thicker than the chip (10), and the sealing insulator (66) is thicker than the chip (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishimura with Hikasa by providing a terminal electrode and sealing insulator thicker than the chip in order to provide mechanical support, prevent electromigration under high current densities, and act as an integrated heat sink.
Regarding claim 14, Nishimura fails to disclose a semiconductor device further comprising: an insulating film that partially covers the main surface electrode; wherein the sealing insulator has a portion that covers the main surface electrode with the insulating film interposed therebetween.
However, Hikasa teaches a semiconductor device further comprising: an insulating film (63) that partially covers the main surface electrode (55); wherein the sealing insulator (66) has a portion that covers the main surface electrode with the insulating film interposed therebetween (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishimura with Hikasa by providing a sealing insulator that partially convers the main surface electrode such that an insulating film is interposed therebetween in order to prevent delamination and moisture ingress caused by thermal expansion mismatching.
Regarding claim 15, Nishimura fails to disclose a semiconductor device wherein the terminal electrode has a portion that directly covers the insulating film.
However, Hikasa teaches a semiconductor device wherein the terminal electrode (75) has a portion that directly covers the insulating film (63) (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishimura with Hikasa by providing a terminal electrode partially covering the insulating film in order to provide a field plate that neutralizes destructive electric field concentrations.
Regarding claim 16, Nishimura fails to disclose a semiconductor device wherein the insulating film includes either or both of an inorganic insulating film and an organic insulating film.
However, Hikasa teaches a semiconductor device wherein the insulating film (63, Fig. 2) includes either or both of an inorganic insulating film and an organic insulating film (par. 0136).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishimura with Hikasa by implementing an insulating film that is either organic or inorganic in order to provide either superior elasticity to prevent delamination or superior dielectric strength to act as a barrier against moisture and high voltage breakdown.
Regarding claim 17, Nishimura fails to disclose a semiconductor device wherein the chip has a laminated structure that includes a substrate and an epitaxial layer, and includes the main surface that is formed by the epitaxial layer.
However, Hikasa teaches a semiconductor device wherein the chip (10, Fig. 1) has a laminated structure (par. 0057) that includes a substrate (13, Fig. 1) and an epitaxial layer (14, Fig. 1), and includes the main surface (11, Fig. 1) that is formed by the epitaxial layer.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishimura with Hikasa by providing a laminated structure for the substrate and epitaxial layer in order to combine a thick, highly conductive base for mechanical support and current flow.
Regarding claim 18, Nishimura fails to disclose a semiconductor device wherein the epitaxial layer is thicker than the substrate.
However, Hikasa teaches a semiconductor device wherein the epitaxial layer (14) is thicker than the substrate (13) (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishimura with Hikasa by providing an epitaxial layer that is thicker than the substrate in order to allow a wide drift region that can sustain high blocking voltages and to minimize electrical and thermal resistance.
Regarding claim 19, Nishimura fails to disclose a semiconductor device wherein the chip has a single layered structure that consists of an epitaxial layer.
However, Hikasa teaches a semiconductor device wherein the chip (10, Fig. 1) has a single layered structure that consists of an epitaxial layer (14, Fig. 1) (par. 0057).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishimura with Hikasa by providing a single layered structure consisting of an epitaxial layer in order to implement a highly optimized active region for switch and voltage control.
Conclusion
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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