DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 51 – 52 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 51 recites the limitation, “the solder joint having tapered sidewalls diminishing from the second width at an interface with the second contact pad to a third width less than the second width at an interface with the first contact pad,” however as currently written it seems as if the second width is at the interface of the second contact pad, not the first contact pad. Further, it seems as if the third width is at the interface with the first contact pad. However, the second width corresponds with the first contact pad not the second contact pad. In an effort of compact prosecution, the Examiner will interpret the second width to correspond to the planar contact surface.
Claim 52 is rejected by virtue of its dependency of claim 51.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-25, and 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. [US 2014/0117532 A1],”Chuang” in view of Chen et al. [US 2011/0193232 A1], “Chen” and further in view of Lee et al. [US 2003/0127734 A1], “Lee”.
Regarding claim 21, Chuang discloses a method (Fig. 1A – 2, See annotated Fig. 1F below for addition reference identification for clarity) comprising:
forming on a first semiconductor device (Fig. 1E/1F, 202) a first contact pad (208(a)) having a first internal surface (FIS) and having a first contact surface (FCS) (¶[0013]-¶[0016]);
forming a solder layer (Fig. 1E, 208(b)) onto the first contact surface (¶[0016]);
forming on a second semiconductor device (102) a second contact pad (116) having a second internal surface (SIS) and a second contact surface (SCS);
wherein the first internal surface (FIS) of the first contact pad (208(a)) has a first width (W1), the first contact surface (FCS) of the first contact pad (208(a)) has a second width (W2), the second internal surface (SIS) of the second contact pad (116) has a third width (W3), and the second contact surface (SCS) of the second contact pad (116) has a fourth width (W4) less than (as shown in Fig. 1F) the second width (W2);
aligning the first contact pad (208(a)) and the second contact pad (116) to bring the solder layer (208(b)) into contact with the second contact surface (SCS) (as shown in Fig. 1E and 1F and ¶[0017]); and
performing a thermal process (¶[0017] teaches a reflow process ) to cause the solder layer to form a solder joint bonding the first contact pad to the second contact pad (as shown in Fig. 1F), the solder joint having tapered sidewalls diminishing from the second width (W2) at an interface with the first contact pad (208(a)) to the fourth width (W4) at an interface with the second contact pad (as shown in Fig. 1F).
Chuang discloses dimensions and characteristics of the bump interconnection structure (210) can be optimized in order to improve yield and bond integrity of the packaging assembly (¶[0018] of Chuang). Chuang does not explicitly disclose a ratio of the first width to the second width is about 2:5.
However, Chen teaches a conductive pillar structure with a first internal surface (Fig. 6, 129a) having a first width (127) and the first contact surface (129b) has a second width (133). Chen further discloses the ratio of first width (127) to second width (133) is between about 0.35 and about 0.65 (¶[0027]). Chen discloses optimizing the size of pillar will help prevent delamination and cracking and further strengthen the bonding between
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the ratio the width of the contact surface with relation to the width of the internal surface of the contact pad of as taught in Chen in the device of Chuang such that a ratio of the first width to the second width is about 2:5 because such a modification of optimizing the size of the contact pad would reduce interconnection failure between substrate and the contact pad while improving yield and bond integrity of the packaging assembly (¶[0005] and ¶[0027] of Chen). Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Chuang discloses the solder layer (208b) is formed by suitable processes (¶[0016]). Further, Chuang discloses metal layer (114) is deposited by plating (¶[0011]). Chuang does not the solder layer was form by plating.
However, Lee disclose a forming a bonding structure (Fig. 2D, 260) in which an electroplating operation is conducted to deposit conductive material (240) into the opening (232). Further, an electroplating operation or a printing operation is conducted to fill the remaining space of the opening (232) with solder material using the conductive cylinder (240) as a seed layer (¶[0031]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use known technique as an electroplating process as taught in Lee in the device of Chuang as modified such that the solder layer was form by electroplating because the process will form bonding structure capable of reducing the separation between neighboring bonding pads on a chip while increasing distance of separation between the chip and a substrate (¶[0012] of Lee).
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Regarding claim 22, Chuang as modified discloses claim 21, Chuang further discloses the thermal process is a solder reflow process (¶[0017] teaches a reflow process ).
Regarding claim 23, Chuang as modified discloses claim 21, Chuang as modified by Lee further discloses the step of plating the solder layer onto the first contact surface is a process selected from the group consisting of electroplating, evaporation, printing, and solder transfer (Chuang as modified by Lee discloses electroplating ¶[0031] of Lee. Also see claim 21).
Regarding claim 24, Chuang as modified discloses claim 21, Chuang as modified further discloses the step of plating the solder layer(208(b)) onto the first contact surface results in the solder layer having a top surface shape that matches a top surface shape of the first contact pad (208(a)) - (as shown).
Regarding claim 25, Chuang as modified discloses claim 21, Chuang as modified further discloses the step of forming on the first semiconductor device (Fig. 1E, 202) the first contact pad (208(a)), results in the first contact pad being in physical and electrical contact (through the use of contact pad (204)) with an integrated passive device of the first semiconductor device (¶[0013] teaches passive devices such as capacitors and inductors).
Regarding claim 27, Chuang as modified discloses claim 21, Chuang as modified further discloses the step of forming on the first semiconductor device (Fig. 1E, 202) the first contact pad (208(a)), includes forming the first contact pad to extend over a portion of an outermost surface of the first semiconductor device ( as shown in Fig. 1E).
Regarding claim 28, Chuang as modified discloses claim 21, Chuang as modified further discloses the third width is greater than the first width ( as shown in annotated Fig 1E).
Regarding claim 29, Chuang as modified discloses claim 21, Chuang as modified further discloses the step of forming on the second semiconductor device (Fig. 1E, 102) a second contact pad (116), includes forming an encapsulant (106) over a redistribution layer (RDL) (104, ¶[0009]), patterning the encapsulant to form a recess (110) exposing the RDL (104), and depositing metal ( 114) to fill the recess (110) (see Fig. 1A- 1D).
Claims 43, 45, and 48-50 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. [US 2014/0117532 A1],”Chuang” in view of Chen et al. [US 2011/0193232 A1], “Chen”.
Regarding claim 43, Chuang discloses a method (Fig. 1A – 2, See annotated Fig. 1F above for addition reference identification for clarity) comprising:
providing a first semiconductor device (Fig. 1E/1F, 202 and 206) having on a surface (as shown) thereof a first contact pad (208(a)), wherein the first contact pad (208(a)) has a first internal connection surface (FIS) that has a first width (W1) and has a first contact surface (FCS) that has a second width (W2) greater (as shown) than the first width (W1);
depositing (as shown in Fig. 1E) on the first contact surface (FCS) of the first contact pad (208(a)) a solder layer (Fig. 1E, 208(b)), the solder layer having the second width (W2) at an interface with the first contact surface of the first contact pad (as shown in Fig 1F);
providing a second semiconductor device (102) having a second contact pad (116) with a second internal connection surface second contact surface (SIS) that has a third width (W3) and a second contact surface (SCS) having a fourth width (W4) less than the second width (S2) – as shown;
wherein at least one of the first contact surface and the second contact surface is planar (the first contact surface is planar);
aligning the first semiconductor device and the second semiconductor device to bring the solder layer into contact with the second contact pad (as shown in Fig. 1E and 1F and ¶[0017]); and
performing a thermal process (¶[0017] teaches a reflow process ) to cause the solder layer to form a solder joint bonding the first contact pad to the second contact pad (as shown in Fig. 1E).
Chuang discloses dimensions and characteristics of the bump interconnection structure (210) can be optimized in order to improve yield and bond integrity of the packaging assembly (¶[0018] of Chuang). Chuang does not explicitly disclose and wherein a ratio of the first width to the second width is 2:5 when the first contact surface is planar.
However, Chen teaches a conductive pillar structure with a first internal surface (Fig. 6, 129a) having a first width (127) and the first contact surface (129b) has a second width (133). Chen further discloses the ratio of first width (127) to second width (133) is between about 0.35 and about 0.65 (¶[0027]). Chen discloses optimizing the size of pillar will help prevent delamination and cracking and further strengthen the bonding between
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the ratio the width of the contact surface with relation to the width of the internal surface of the contact pad of as taught in Chen in the device of Chuang such that a ratio of the first width to the second width is about 2:5 when the first contact surface is planar because such a modification of optimizing the size of the contact pad would reduce interconnection failure between substrate and the contact pad while improving yield and bond integrity of the packaging assembly (¶[0005] and ¶[0027] of Chen). Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233.
Regarding claim 45, Chuang as modified discloses claim 43, Chuang discloses the solder joint (208(b)) diminished in width from the second width (W2) to the fourth width (W4) ( as shown in annotated Fig 1E).
Regarding claim 48, Chuang as modified discloses claim 43, Chuang disclose the step of providing the second semiconductor device (Fig. 1E, 102) having the second contact pad (116), includes forming a redistribution layer (104, ¶[0009]) in the second semiconductor device and electrically contacting the second contact pad to the redistribution layer (as shown).
Regarding claim 49, Chuang as modified discloses claim 43, Chuang further discloses the step of providing the first semiconductor device (Fig. 1E, 202 and 206) having on the surface thereof the first contact pad (208(a)), includes forming an integrated passive device(204 and ¶[0014]) in the first semiconductor device, forming a recess (206) in an outer surface of the first semiconductor device to expose the integrated passive device (204), and forming the first contact pad within the recess (as shown).
Regarding claim 50, Chuang as modified discloses claim 43, Chuang further discloses forming the first contact pad (208(a)) to extend (as shown in Fig. 1F) over a portion of the outer surface of the first semiconductor device (Fig. 1E, 202 and 206) .
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. [US 2014/0117532 A1],”Chuang” in view of Chen et al. [US 2011/0193232 A1], “Chen” and Lee et al. [US 2003/0127734 A1], “Lee” as applied to claim 25 and further in view of Chou et al. [US 2005/0017355 A1], “Chou”.
Regarding claim 26, Chuang as modified discloses claim 25, Chuang as modified further discloses the step of forming on the first semiconductor device (Fig. 1E, 202) the first contact pad (208(a)), includes recessing a portion of the first semiconductor device to form a recess exposing the integrated passive device (forming an opening in the layer (206) in order to make an opening to the device interconnection layer (204) - ¶[0016])). Contact pad (208(a)) is formed of copper, which is referred to as a copper bump (¶[0016]). Chuang as modified does not disclose forming a seed layer on the integrated passive device, and depositing a metal layer in the recess.
However, Chou discloses the wafer (Fig. 9, 10) includes a semiconductor substrate and semiconductor device structures connected to bond pads (21). The bonding pads can be used for inputting/outputting of signal and power sources and for interconnection to other devices in a package. Within a recess formed to expose the bonding pads, a seed layer (40) is form on the bonding pads (¶[0033]). Caps (Fig. 9, 48) are formed on the seed layer.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a seed layer as taught in Chou in the device of Chuang as modified such that a seed layer on the integrated passive device, and depositing a metal layer in the recess because using a seed layer can used to help prevent diffuses and cracks in the cap layer and aid in forming better electrically connect to the external circuit (¶[0014] of Chou).
Claim 42 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. [US 2014/0117532 A1],”Chuang” in view of Chen et al. [US 2011/0193232 A1], “Chen” and Lee et al. [US 2003/0127734 A1], “Lee” as applied to claim 22 and further in view of Kuo [US 2011/0193220 A1], “Kuo”.
Regarding claim 42, Chuang discloses claim 22, and Chuang the step of performing the thermal process (¶[0017] teaches a reflow process ). Chuang as modified does not disclose the second contact surface has a concavity therein, and wherein the step of performing the thermal process causes the solder layer to fill the concavity.
However Kuo discloses an alternative non-planar surface for the conductive pillar (Fig. 4, 410). Kuo discloses the top surface may be concave, convex, or wave shaped. Further, the solder joint (Fig. 6, 610) to conform to the concave contact surface.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create a concave surface as taught in Kuo in the device of Chuang as modified such that the second contact surface has a concavity therein, and wherein the step of performing the thermal process causes the solder layer to fill the concavity because this structural shape can reduce cracking thus providing a better electrical connection between the solder and the pillar (¶[0028] of Kuo). (Chuang discloses the thermal process and Kuo teaches a solder layer can be formed over the concave surface – see claim 51).
Claim 44 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. [US 2014/0117532 A1],”Chuang” in view of Chen et al. [US 2011/0193232 A1], “Chen” as applied to claim 43 and further in view of Kuo [US 2011/0193220 A1], “Kuo”.
Regarding claim 44, Chuang discloses claim 43, and the step of performing the thermal process (¶[0017] teaches a reflow process ). Chuang as modified does not disclose the second contact surface has a concavity therein, and wherein the step of performing the thermal process causes the solder layer to fill the concavity.
However Kuo discloses an alternative non-planar surface for the conductive pillar (Fig. 4, 410). Kuo discloses the top surface may be concave, convex, or wave shaped. Further, the solder joint (Fig. 6, 610) to conform to the concave contact surface.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create a concave surface as taught in Kuo in the device of Chuang as modified such that the second contact surface has a concavity therein, and wherein the step of performing the thermal process causes the solder layer to fill the concavity because this structural shape can reduce cracking thus providing a better electrical connection between the solder and the pillar (¶[0028] of Kuo). (Chuang discloses the thermal process and Kuo teaches a solder layer can be formed over the concave surface – see claim 51).
Claim 46 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. [US 2014/0117532 A1],”Chuang” in view of Chen et al. [US 2011/0193232 A1], “Chen” as applied to claim 43 and further in view of Endo [US 2009/0188706 A1].
Regarding claim 46, Chuang discloses claim 43, Chuang as modified does not discloses the solder layer, as deposited, has a substantially planar outer surface.
However, Endo discloses an alternative solder bump structure. Endo discloses the bump (2) is formed on a metal layer (Fig. 5C, 1). The bump (Fig. 5C, 2) has planar outer surface. The bump is then joined to conductive layer (43).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a suitable alternative shape for the solder as taught in Endo in the device of Chuang as modified such that the solder layer, as deposited, has a substantially planar outer surface because having the solder layer with the proper shape and height will allow for improved electrical connection for electronic components (¶[0033]-¶[0034]). Further, the change in shape has been held a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed device was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP 2144.04).
Claim 47 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. [US 2014/0117532 A1],”Chuang” in view of Chen et al. [US 2011/0193232 A1], “Chen” as applied to claim 43 and further in view of Chou et al. [US 2005/0017355 A1], “Chou”.
Regarding claim 47, Chuang as modified discloses claim 43, Chuang discloses the step of providing the first semiconductor device (Fig. 1F, 202 and 206) having on the surface thereof the first contact pad (208(a)), includes forming a recess (recess in 206) in an outer surface of the first semiconductor device (as shown), the recess exposing an electrical device (204 and ¶[0014]), Chuang as modified does not discloses filling the recess with a metal, wherein the metal extends over a portion of the outer surface of the first semiconductor device.
However, Chou discloses the wafer (Fig. 9, 10) includes a semiconductor substrate and semiconductor device structures connected to bond pads (21). The bonding pads can be used for inputting/outputting of signal and power sources and for interconnection to other devices in a package. Within a recess formed to expose the bonding pads, a seed layer (40) is form on the bonding pads (¶[0033]). Caps (Fig. 9/10, 48) are formed on the seed layer.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a seed layer as taught in Chou in the device of Chuang as modified such that a seed layer on the integrated passive device, and depositing a metal layer in the recess because using a seed layer can used to help prevent diffuses and cracks in the cap layer and aid in forming better electrically connect to the external circuit (¶[0014] of Chou).
Claims 51-52 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. [US 2014/0117532 A1],”Chuang” in view of Chen et al. [US 2011/0193232 A1], “Chen” in view of Lee et al. [US 2003/0127734 A1], “Lee” and further in view of Kuo [US 2011/0193220 A1], “Kuo”.
Regarding claim 51, Chuang discloses a method (Fig. 1A – 2, See annotated Fig. 1F above for addition reference identification for clarity) comprising:
forming on a first semiconductor device (Fig. 1E/1F, 202) a first contact pad (208(a)) having a first internal surface (FIS) and having a planar contact surface (FCS) (¶[0013]-¶[0016]);
forming a solder layer (Fig. 1E, 208(b)) onto the planar contact surface (FCS) (¶[0016]);
forming on a second semiconductor device (102) a second contact pad (116) having a second internal surface (SIS);
wherein the first internal surface (FIS) of the first contact pad (208(a)) has a first width (W1), the planar contact surface (FCS) of the first contact pad (208(a)) has a second width (W2);
aligning the first contact pad (208(a)) and the second contact pad (116) to bring the solder layer (208(b)) into contact with the contact surface (as shown in Fig. 1E and 1F and ¶[0017]); and
performing a thermal process (¶[0017] teaches a reflow process ) to cause the solder layer to form a solder joint bonding the first contact pad to the second contact pad (as shown in Fig. 1F), the solder joint having tapered sidewalls diminishing from the second width (W2) at an interface with the second contact pad to a third width (W3) less than the second width at an interface with the first contact pad (see 112 rejection above).
Chuang discloses dimensions and characteristics of the bump interconnection structure (210) can be optimized in order to improve yield and bond integrity of the packaging assembly (¶[0018] of Chuang). Chuang does not explicitly disclose a ratio of the first width to the second width is about 2:5.
However, Chen teaches a conductive pillar structure with a first internal surface (Fig. 6, 129a) having a first width (127) and the first contact surface (129b) has a second width (133). Chen further discloses the ratio of first width (127) to second width (133) is between about 0.35 and about 0.65 (¶[0027]). Chen discloses optimizing the size of pillar will help prevent delamination and cracking and further strengthen the bonding between
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the ratio the width of the contact surface with relation to the width of the internal surface of the contact pad of as taught in Chen in the device of Chuang such that a ratio of the first width to the second width is about 2:5 because such a modification of optimizing the size of the contact pad would reduce interconnection failure between substrate and the contact pad while improving yield and bond integrity of the packaging assembly (¶[0005] and ¶[0027] of Chen). Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233.
Chuang discloses the solder layer (208b) is formed by suitable processes (¶[0016]). Further, Chuang discloses metal layer (114) is deposited by plating (¶[0011]). Chuang does not the solder layer was form by plating.
However, Lee disclose a forming a bonding structure (Fig. 2D, 260) in which an electroplating operation is conducted to deposit conductive material (240) into the opening (232). Further, an electroplating operation or a printing operation is conducted to fill the remaining space of the opening (232) with solder material using the conductive cylinder (240) as a seed layer (¶[0031]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use known technique as an electroplating process as taught in Lee in the device of Chuang as modified such that the solder layer was form by electroplating because the process will form bonding structure capable of reducing the separation between neighboring bonding pads on a chip while increasing distance of separation between the chip and a substrate (¶[0012] of Lee).
Chuang as modified does not disclose a concave contact surface.
However Kuo discloses an alternative non-planar surface for the conductive pillar (Fig. 4, 410). Kuo discloses the top surface may be concave, convex, or wave shaped. Further, the solder joint (Fig. 6, 610) to conform to the concave contact surface.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create a concave surface as taught in Kuo in the device of Chuang as modified such that the second contact pad includes a concave contact surface because this structural shape can reduce cracking thus providing a better electrical connection between the solder and the pillar (¶[0028] of Kuo).
Regarding claim 52, Chuang as modified discloses claim 51 and Chuang as modified discloses forming the thermal process causes the solder joint to conform to the concave contact surface (Chuang discloses the thermal process and Kuo teaches a solder layer can be formed over the concave surface – see claim 51).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection required by Applicant’s amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoon et al. [US 2006/0223313 A1] discloses a taper interconnection between semiconductor chips and substrates.
Endo [US 2009/0188706 A1] discloses a tapered solder structure.
Daizo et al. [US 2015/0255433 A1] discloses a solder connection between two substrates.
Tai et al. [US 2015/0048499 A1] disclose fine-pitch pillar bump layout structure on chip.
Liao et al. [US 2014/0061906 A1] disclose conductive pillar with a concave structure.
Greer [US 5,470,787 A] disclose a solder bump with tapered sides.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/P.M.R/Examiner, Art Unit 2897
/MARK W TORNOW/Primary Examiner, Art Unit 2891