DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/24/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-6 and 8- 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2022/093593), and further in view of Chanemougame (2022/102362).
Regarding claim 1, Yang teaches a three-dimensional (3D) static random access memory (SRAM) cell in figs. 16-19 and 22, comprising:
two pull-up (PU) transistors arranged in a first tier of the 3D SRAM cell (T1, T4 in tier T1 as shown in fig. 16);
two pull-down (PD) transistors arranged in a second tier of the 3D SRAM cell, the second tier being arranged above or below the first tier (T2, T5 in tier T2 s shown in fig. 16),
wherein the two PU transistors and the two PD transistors form a pair of cross-coupled inverters (see fig. 18, 19); and
two pass gate (PG) transistors (T3, T6) arranged in the first tier or in the second tier (T3 as the same tier as T2).
Yang does not teach “wherein: each of the PU, PD and PG transistors is a fin transistor, each PU transistor has a first number of fins, each PD transistor has a second number of fins, and wherein a ratio of the first number to the second number is 2:1 and the PG transistors are arranged in the first tier, or the ratio of the first number to the second number is 1:2 and the PG transistors are arranged in the second tier, or
each of the PU, PD and PG transistors is a nanosheet-based transistor, each PU transistor has a first nanosheet width, each PD transistor has a second nanosheet width, and wherein a ratio of the first nanosheet width to the second nanosheet width is 2:1 and the PG transistors are arranged in the first tier, or the ratio of the first nanosheet width to the second nanosheet width is 1:2 and the PG transistors are arranged in the second tier.”
Chanemougame teaches the same field of an endeavor wherein each of the PU, PD and PG transistors is a fin transistor, a ratio of first number fin of PU transistor to second number fins of the PG transistor is 1:2 (see par. 83).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include each of the PU, PD and PG transistors is a fin transistor, each PU transistor has a first number of fins, each PD transistor has a second number of fins, and wherein a ratio of the first number to the second number is 2:1 and the PG transistors are arranged in the first tier, or the ratio of the first number to the second number is 1:2 and the PG transistors are arranged in the second tier as taught by Chanemougame in the teaching of Yang so that the SRAM speed can be optimize by fine tuning the PU: PD:PG drive strength in a ratio of 1:2:2 (see par. 83).
Regarding claim 2, Yang and Chanemougame teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chanemougame teaches each of the PU, PD and PG transistors is the fin transistor, each PG transistor includes a third number of fins, and the third number of fins is equal to the first number or to the second number (see par. 83); or each of the PU, PD and PG transistors is the nanosheet-based transistor, and each PG transistor includes a third nanosheet width, and the third nanosheet width is equal to the first nanosheet width or the second nanosheet width.
Regarding claim 3, Yang and Chanemougame teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chanemougame teaches the SRAM cell is a high performance SRAM cell, and wherein: each of the PU, PD and PG transistors is the fin transistor, a fin ratio of the first number to the third number and to the second number is 2:2:1 and the PG transistors are arranged in the first tier, or the fin ratio is 1:2:2 and the PG transistors are arranged in the second tier, or each of the PU, PD and PG transistors is the nanosheet-based transistor, a width ratio of the first nanosheet width to the third nanosheet width and to the second nanosheet width is 2:2:1 and the PG transistors are arranged in the first tier, or the width ratio is 1:2:2 and the PG transistors are arranged in the second tier (see par. 83).
Regarding claim 5, Yang and Chanemougame teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chanemougame teaches each PD transistor in the second tier is stacked directly above or below one of the PU transistors in the first tier, and each pair of one PU transistor in the first tier and one PD transistor in the second tier is based on a complementary field effect transistor, CFET (see fig. 19 or the above claim 1’s rejection).
Regarding claim 6, Yang and Chanemougame teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chanemougame teaches the PG transistors are arranged in the first tier, the PG transistors and the PU transistors in the first tier are p-type metal-oxide-semiconductor transistors (PMOS), and the PD transistors in the second tier are n-type metal-oxide-semiconductor (NMOS) transistors; or the PG transistors are arranged in the second tier, the PG transistors and the PD transistors in the second tier are n-type NMOS transistors, and the PU transistors in the first tier are PMOS transistors (see fig. 19).
Regarding claim 8, Yang teaches method of fabricating a three-dimensional (3D) static random access memory (SRAM) cell in figs. 16-19 and 22, the method comprising:
forming two pull-up (PU) transistors in a first tier of the 3D SRAM cell (T1 and T4) (see fig. 16);
forming two pull-down (PD) transistors in a second tier of the 3D SRAM cell, the second tier being formed below or above the first tier (T2 and T5) (in fig. 16);
forming two pass gate (PG) transistors in the first tier or the second tier; connecting the two PU transistors and the two PD transistors to form a pair of cross-coupled inverters (see fig. 18, 19).
Yang fails to teach “wherein: each of the PU, PD and PG transistors is a fin transistor, each PU transistor is formed to have a first number of fins, each PD transistor is formed to have a second number of fins, and a ratio of the first number to the second number is 2:1 and the PG transistors are arranged in the first tier, or the ratio of the first number to the second number is 1:2 and the PG transistors are arranged in the second tier; or each of the PU, PD and PG transistors is a nanosheet-based transistor, each PU transistor is formed to have a first nanosheet width, each PD transistor is formed to have a second nanosheet width, and a ratio of the first to the second nanosheet width is 2:1 and the PG transistors are arranged in the first tier, or the ratio of the first to the second nanosheet width is 1:2 and the PG transistors are arranged in the second tier.”
Chanemougame teaches the same field of an endeavor wherein each of the PU, PD and PG transistors is a fin transistor, a ratio of first number fin of PU transistor to second number fins of the PG transistor is 1:2 (see par. 83).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include each of the PU, PD and PG transistors is a fin transistor, each PU transistor has a first number of fins, each PD transistor has a second number of fins, and wherein a ratio of the first number to the second number is 2:1 and the PG transistors are arranged in the first tier, or the ratio of the first number to the second number is 1:2 and the PG transistors are arranged in the second tier as taught by Chanemougame in the teaching of Yang so that the SRAM speed can be optimize by fine tuning the PU: PD:PG drive strength in a ratio of 1:2:2 (see par. 83).
Regarding claim 9, Yang and Chanemougame teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chanemougame teaches each transistor is the fin transistor, each PG transistor is formed to have a third number of fins, and the third number of fins is equal to the first number or to the second number; or each transistor is the nanosheet-based transistor, each PG transistor includes a third nanosheet width, and the third nanosheet width is equal to the first or the second nanosheet width (see claim 2’s rejection).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2022/093593) in view of Chanemougame (2022/102362) as applied to claim 1, and further in view of Liebmann (US 2022/181453).
Regarding claim 7, Yang and Chanemougame teach all the limitations of the claimed invention for the same reasons as set forth above except for the two PU transistors and the two PD transistors form a pair of cross-coupled inverters, and wherein a cross-coupling structure for the pair of cross-coupled inverters is arranged in the second tier directly above or below each of the PG transistors.
Liebmann teaches the same field of an endeavor wherein a stacked nanosheet SRAM with two tiers (device planes) wherein at least part of the cross-coupling structure (270) is located directly above the PG transistor (210).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the two PU transistors and the two PD transistors form a pair of cross-coupled inverters, and wherein a cross-coupling structure for the pair of cross-coupled inverters is arranged in the second tier directly above or below each of the PG transistors as taught by Liebmann in the combined teaching of Yang and Chanemougame because stacking the pull up/pull down devices above the PG and placing the cross coupling structure directly above them drastically shortens the vertical distance, freeing up routing resources on the dense bottom tiers and reducing parasitic.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the SRAM cell is for a low power SRAM cell, and wherein: each transistor is the fin transistor, the fin ratio of the first number to the third number to the first second number is 2:1:1 and the PG transistors are arranged in the first tier, or the fin ratio is 1:1:2 and the PG transistors are arranged in the second tier, or each transistor is the nanosheet-based transistor, the width ratio of the first nanosheet width to the third nanosheet width and to the first second nanosheet width is 2:1:1 and the PG transistors are arranged in the first tier, or the width ratio is 1:1:2 and the PG transistors are arranged in the second tier.”
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “forming two intermediate transistors in the second tier or first tier directly above or below the PG transistors in the first tier or second tier, respectively; removing at least a part of a channel structure of each intermediate transistor; and forming a cross-coupling structure for the pair of cross-coupled inverters in spaces created by removing the at least part of the channel structure of each intermediate transistor.”
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the PU, PD and PG transistors are fin transistors, and the method comprises: initially forming each PD transistor in the second tier with a same number of fins as the PU transistors in the first tier, and removing at least one fin of each PD transistor, so as to reduce the number of fins of the PD transistor to the second number, wherein the PG transistors are arranged in the first tier, or removing at least one fin of each PU transistor, so as to reduce the number of fins of the PU transistor to the first number, wherein the PG transistors are arranged in the second tier.” Claims 12, 15 include all the limitations of claim 11.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “ach transistor is nanosheet-based transistors, and wherein the method further comprising: initially forming each PD transistor in the second tier with a same nanosheet width as the PU transistors in the first tier; and reducing the nanosheet width of each PD transistor by isotropic trimming to the second nanosheet width and the PG transistors are arranged in the first tier, or reducing the nanosheet width of each PU transistor by isotropic trimming to the first nanosheet width and the PG transistors are arranged in the second tier.” Claims 14 and 16 include all the limitations of claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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