Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-12, 15-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagata (WO 2020/213603 A1).
Regarding claim 1, Nagata discloses a semiconductor device comprising:
a chip (2) having a main surface (top surface 3) [Fig. 2];
a main surface electrode (15 or 14) arranged on the main surface [Fig. 2];
a terminal electrode (16 and/or 23, respectively) that has a terminal surface (interface between 16 and 25 or surface 24, respectively) and a terminal side wall (interface between 16 and 17 or interface between 17 and 23, respectively), and that has a recessed portion (portion located within opening 13 or portion located within opening 18, respectively) recessed toward the main surface electrode side in the terminal surface [Fig. 2]; and
a sealing insulator (12, 19 and/or 20) that covers a periphery of the terminal electrode (16 and/or 23) on the main surface such as to expose the terminal surface (interface between 16 and 23 or surface 24, respectively) and cover the terminal side wall [Fig. 2].
Regarding claim 2, Nagata discloses wherein the sealing insulator (12 and 17) has a portion (17) that covers the recessed portion (portion 16 located within opening 13) [Fig. 2].
Regarding claim 5, Nagata discloses wherein the recessed portion (16) is formed at a corner portion of the terminal surface (interface between 16 and 25) such as to define a step portion (Step) in the terminal side wall [Fig. 2, annotated below].
[AltContent: textbox (Top Planar Area)][AltContent: ][AltContent: textbox (Step)][AltContent: arrow]
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Regarding claim 6, Nagata discloses wherein the recessed portion (16) is formed in an annular shape (13) extending along a peripheral edge of the terminal surface (interface between 16 and 25) such as to surround an inner portion of the terminal surface (interface between 16 and 25) in plan view [Fig. 1].
Regarding claim 7, Nagata discloses wherein the terminal electrode (16 and 23) includes a first layer portion (16) that is positioned on the main surface electrode side (15) and a second layer portion (23) that protrudes toward the opposite side with respect to the chip (2) from the first layer portion (16) such as to define the recessed portion with the first layer portion (16) and has the terminal surface (24) that is formed by the second layer portion (23) [Fig. 2], and
the sealing insulator (12 and 17) covers the second layer portion (23) and the first layer portion (16) such as to expose the terminal surface (24) [Fig. 2].
Regarding claim 8, Nagata discloses wherein the first layer portion (16) has a first planar area (Top Planar Area including interfaces 16/19 and 16/25), and the second layer portion (23) has a second planar area (24) that is less than the first planar area (Top Planar Area) [Fig. 2, annotated above].
Regarding claim 9, Nagata discloses wherein the first layer portion (16) has a first thickness, and the second layer portion (23) has a second thickness exceeding the first thickness [Fig. 2].
Regarding claim 10, Nagata discloses wherein the first layer portion (16) has a first thickness, and the second layer portion (27) has a second thickness less than the first thickness [Fig. 2].
Regarding claim 11, Nagata discloses wherein the sealing insulator (12 and 17) has a laminated structure including a first sealing insulator (19) that covers a periphery of the first layer portion (16) on the main surface and a second sealing insulator (20) that covers a periphery of the second layer portion (23) on the first sealing insulator [Fig. 2].
Regarding claim 12, Nagata discloses wherein the first layer portion (16) has a first layer main surface (Top Planar Area) and a first layer side wall (edges after the Top Planar Area), the second layer portion (23) has a second layer main surface (24) and a second layer side wall (along edges 21/22) [Fig. 2, annotated above],
the first sealing insulator (19) covers a periphery of the first layer portion on the main surface such as to expose the first layer main surface and cover the first layer side wall [Fig. 2], and
the second sealing insulator (20) covers a periphery of the second layer portion (23) on the first sealing insulator such as to expose the second layer main surface (24) as the terminal surface and cover the second layer side wall [Fig. 2].
Regarding claim 15, Nagata discloses an insulating film (12) that covers the main surface electrode (portion 15 located within opening13); wherein the terminal electrode (16) has a portion that covers the insulating film (12) [Fig. 2].
Regarding claim 16, Nagata discloses wherein the sealing insulator (17) has a portion that covers the insulating film (12) [Fig. 2].
Regarding claim 17, Nagata discloses wherein the chip (2) has a laminated structure including a substrate (6) and an epitaxial layer (7), and includes the main surface (3) that is formed by the epitaxial layer [Fig. 2]
Regarding claim 19, Nagata discloses wherein the chip (7) has a single layered structure consisting of an epitaxial layer [Fig. 2].
Regarding claim 20, Nagata discloses wherein the chip (2) includes a monocrystal of a wide bandgap semiconductor (SiC) [See the SiC chip 2 description in the DESCRIPTION-OF-EMBODIMENTS section of the Machine English Translation].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata (WO 2020/213603 A1).
Regarding claim 3, Nagata discloses wherein the terminal electrode (layer 16 has a thickness of 10 μm; layer 25 has a thickness of 10 μm; layer 26 has a thickness of 10 μm; and layer 27 has a thickness of 3 μm ) is thicker than the chip (consider the epitaxial layer 7 as the chip layer having a thickness of 1 μm) [See DESCRIPTION-OF-EMBODIMENTS section of the Machine English Translation]. The court has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541F.2d 257,191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 4, Nagata discloses wherein the sealing insulator (layer 19 has a thickness of 20 μm, and layer 20 has a thickness of 50 μm) is thicker than the chip (layer 6 has a thickness of 40 μm and layer 7 has a thickness of 1 μm) [See DESCRIPTION-OF-EMBODIMENTS section of the Machine English Translation]. The court has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541F.2d 257,191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 18, Nagata discloses wherein the epitaxial layer (7) is thicker than the substrate (6) [See DESCRIPTION-OF-EMBODIMENTS section of the Machine English Translation, wherein Nagata, for example, discloses an epitaxial layer (7) having a thickness of 50 μm and a substrate (6) having a thickness of 40 μm]. The court has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541F.2d 257,191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nagata (US 2022/0181447) is the English equivalent to WO 2020/213603 A1; and Nakano et al. (US 2023/0103655) is related to the current application. Also, Uchida (2018/0174938) teaches first and second electrodes (159/112) in Figures 2A-2B].
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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