DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 4, 7 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kini et al. (US 2025/0107045).
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(Claim 1) Kini et al. teach a semiconductor device package, comprising:
a substrate (402);
a plurality of semiconductor dies (204) on a first side of the substrate;
a plurality of integrated circuit devices (208) on a second side of the substrate opposite the first side;
a first vapor chamber lid structure (210) over the plurality of semiconductor dies and thermally coupled with the plurality of semiconductor dies; and
a second vapor chamber lid structure (302) over the plurality of integrated circuit devices and thermally coupled with the plurality of integrated circuit devices (paragraphs 56 – 58).
(Claim 2) Kini et al. teach wherein the plurality of integrated circuit devices comprise a plurality of voltage regulator module (VRM) integrated circuit devices (paragraph 48, PDC); and
wherein the plurality of VRM integrated circuit devices are thermally coupled with the second vapor chamber lid structure by thermal interface material (paragraph 57).
(Claim 3) Kini et al. teach wherein the second vapor chamber lid structure (302) comprises:
a footing (vertical end extensions of 302 abutting 402) having a continuous closed-looped structure that defines a space in which the plurality of integrated circuit devices are located;
a lid coupled (horizontal portion of 302) with the footing and spanning the space defined by the footing,
wherein the lid is thermally coupled with the plurality of integrated circuit devices; and a vapor chamber within the lid (paragraph 58).
(Claim 4) Kini et al. teach wherein the plurality of integrated circuit devices (208) are thermally coupled with a first side of the lid (302); and
wherein the second vapor chamber ( lid structure further comprises a plurality of fins that are physically coupled with a second side of the lid opposing the first side.
(Claim 7) Kini et al. teach wherein a footing (vertical end extensions of 210) of the first vapor chamber lid structure (210) is coupled to the first side (topside) of the substrate (402); and
wherein a footing (vertical end extensions of 302) of the second vapor chamber lid structure is coupled to the second side (underside) of the substrate (402).
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(Claim 15) Kini et al. teach a method, comprising:
attaching a plurality of semiconductor dies (510) to a first side of a substrate (110) of a semiconductor device package;
attaching a thermal lid structure (800) to the first side (topside) of the substrate (1100) such that the thermal lid structure is over the plurality of semiconductor dies and thermally coupled with the plurality of semiconductor dies;
attaching a plurality of integrated circuit devices (602, PDC) to a second side (underside) of the substrate vertically opposite the first side;
dispensing thermal interface material (604) onto the plurality of integrated circuit devices (PDC); and
attaching a vapor chamber lid structure (700) to the second side (underside) of the substrate (1100) such that the vapor chamber lid structure is over the plurality of integrated circuit devices and thermally coupled with the plurality of integrated circuit devices through the thermal interface material.
Claims 8 – 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Singh et al. (US 2019/0045665).
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(Claim 8) Singh et al teach a semiconductor device package, comprising:
a substrate (124);
a plurality of semiconductor dies (122) on a front side of the substrate;
a plurality of voltage regulator integrated circuit devices (128, LSC, paragraph 40) on a back side of the substrate opposing the front side;
a first vapor chamber lid (118, heat spreader, paragraph 40, paragraph 44 heat spreader can be comprised of a vapor chamber) structure over the plurality of semiconductor dies and thermally coupled with the plurality of semiconductor dies;
a second vapor chamber lid structure (138, paragraph 44) over the plurality of voltage regulator integrated circuit devices(128, LSC) and thermally coupled with the plurality of voltage regulator integrated circuit devices; and
one or more package connectors (130) on the back side of the substrate (124),
wherein the one or more package connectors (130) are located outside of a perimeter of the second vapor chamber lid structure (138).
(Claim 9) Singh et al teach wherein the perimeter of the second vapor chamber lid structure (138) is at least partially within a perimeter of the first vapor chamber lid structure (118).
Allowable Subject Matter
Claims 5, 6, 10 – 14 and 16 – 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
July 25, 2026
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